參數(shù)資料
型號: CLA73000
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 2/7頁
文件大小: 105K
代理商: CLA73000
CLA70000V
LOW VOLTAGE SPECIFICATION
1.0
μ
CMOS GATE ARRAYS
AUGUST 1992
FEATURES
I
Operates at 3.3V
I
1.0
μ
(0.8
μ
Leff) twin well, epitaxial CMOS process
I
5,000 to 250,000 available gates on a chanelless
array architecture
I
Low current and power (<1
μ
A/gate/MHz)
I
Slew controlled outputs with drivers up to 12mA for
bus driving and other applications.
I
ESD protection in excess of 2kV
I
Comprehensive cell library including DSP and
compiled memory cells (ROM blocks to 64K bits and
RAM blocks to 16K bits)
I
Supports JTAG/BIST test philosophies
(IEEE 1149-1 Test Procedures)
I
Fully supported on Industry Standard workstations and
in-house software
Description
Page
Process Technology
Core Design
I/O Design
AC Characteristics
2
2
2
3
DC Characteristics
Design Tools
4
5
Packaging
6
ARRAY
RAW GATES
PADS
CLA70000
5000
44
CLA71000
12000
68
CLA72000
19000
84
CLA73000
27000
100
CLA74000
39000
120
CLA75000
70000
160
CLA76000
110000
200
CLA77000
182000
256
CLA78000
256000
304
CLA70000 FAMILY
CONTENTS
GENERAL DESCRIPTION
Advances in processing technology have led to the
development of an array family which can operate at 3 volts.
This series of arrays may be used with the lower voltage
power supply rails which are becoming increasingly common.
Applications include battery portable such as laptop
computers where low power consumption is essential as well
as pagers and consumer applications like hand held language
translators and games. This summary datasheet gives
information on the CLA70000 series AC and DC
characteristics at low voltage.
DS3535 - 1.0
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