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參數(shù)資料
| 型號： | CL7192EQC160-20 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復雜可編程邏輯器件 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 183K |
| 代理商： | CL7192EQC160-20 |
CL7192E and CL7192S Laser Processed Logic Devices
Page 8
AC Electrical Specifications
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
PD1
Input to non-registered output
C
L
= 35 pF
6.0
7.5
10.0
ns
t
PD2
I/O input to non-registered output
C
L
= 35 pF
6.0
7.5
10.0
ns
t
SU
Global clock setup time
4.2
4.1
7.0
ns
t
H
Global clock hold time
-0.8
0.0
0.0
ns
t
FSU
Global clock setup time of fast input
2.5
3.0
3.0
ns
t
FH
Global clock hold time of fast input
0.0
0.0
0.5
ns
t
CO1
Global clock to output delay
C
L
= 35 pF
1.0
3.7
4.7
5.0
ns
t
CH
Global clock high time
3.0
3.0
4.0
ns
t
CL
Global clock low time
3.0
3.0
4.0
ns
t
ASU
Array clock setup time
1.9
1.0
2.0
ns
t
AH
Array clock hold time
1.5
1.8
3.0
ns
t
ACO1
Array clock to output delay
C
L
= 35 pF
6.0
7.8
10.0
ns
t
ACH
Array clock high time
3.0
3.0
4.0
ns
t
ACL
Array clock low time
3.0
3.0
4.0
ns
t
ODH
Output data hold time after clock
C
L
= 35 pF
1.0
1.0
1.0
ns
t
CNT
Minimum global clock period
6.9
8.0
10.0
ns
f
CNT
Max. internal global clock frequency
144.9
125.0
100.0
MHz
t
ACNT
Minimum array clock period
6.9
8.0
10.0
ns
f
ACNT
Max. internal array clock frequency
144.9
125.0
100.0
MHz
7K tbl 06D1
Symbol
Speed: -6
Speed: -7
Speed: -10
I/O Element Timing Parameters
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