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參數(shù)資料
| 型號(hào)： | CL7192EQC160-15 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 183K |
| 代理商： | CL7192EQC160-15 |
CL7192E and CL7192S Laser Processed Logic Devices
Page 11
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
iN
Input pad and buffer delay
0.6
0.3
0.5
ns
t
IO
I/O input pad and buffer delay
0.6
0.3
0.5
ns
t
FIN
Fast input delay
2.7
3.2
1.0
ns
t
SEXP
Shared expander delay
2.5
4.2
5.0
ns
t
PEXP
Parallel expander delay
0.7
1.2
0.8
ns
t
LAD
Logic array delay
2.4
3.1
5.0
ns
t
LAC
Logic control array delay
2.4
3.1
5.0
ns
t
IOE
Internal output enable delay
0.0
0.9
2.0
ns
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer and pad delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer enable delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
t
XZ
Output buffer disable delay
C
L
= 5 pF
[3]
4.0
4.0
5.0
ns
t
SU
Register setup time
1.9
1.1
2.0
ns
t
H
Register hold time
1.5
1.7
3.0
ns
t
FSU
Register setup time of fast input
0.8
2.3
3.0
ns
t
FH
Register hold time of fast input
1.7
0.7
0.5
ns
t
RD
Register delay
1.7
1.4
2.0
ns
t
COMB
Combinatorial delay
1.7
1.2
2.0
ns
t
IC
Array clock delay
2.4
3.2
5.0
ns
t
EN
Register enable time
2.4
3.1
5.0
ns
t
GLOB
Global control delay
1.0
2.5
1.0
ns
t
PRE
Register preset time
3.1
2.7
3.0
ns
t
CLR
Register clear time
3.1
2.7
3.0
ns
t
LIA
LIA delay
1.0
2.4
1.0
ns
7K tbl 07D1
Symbol
t
OD1
C
L
= 35 pF
ns
t
OD2
C
L
= 35 pF
2.0
ns
t
OD3
C
L
= 35 pF
0.9
1.0
5.5
ns
t
ZX1
C
L
= 35 pF
4.0
5.4
4.0
9.0
ns
t
ZX2
C
L
= 35 pF
4.5
4.5
5.0
ns
5.5
ns
t
ZX3
C
L
= 35 pF
9.0
9.0
5.5
Speed: -6
Speed: -7
Speed: -10
0.4
0.5
1.5
AC Electrical Specifications cont.
Internal Timing Parameters
[4]
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