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參數(shù)資料
| 型號： | CL7160STC100-6 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CL7160STC100-6 |
CL7160E and CL7160S Laser Processed Logic Devices
Page 9
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PD1
Input to non-registered output
C
L
= 35 pF
15.0
20.0
ns
t
PD2
I/O input to non-registered output
C
L
= 35 pF
15.0
20.0
ns
t
SU
Global clock setup time
11.0
12.0
ns
t
H
Global clock hold time
0.0
0.0
ns
t
FSU
Global clock setup time of fast input
3.0
5.0
ns
t
FH
Global clock hold time of fast input
0.0
0.0
ns
t
CO1
Global clock to output delay
C
L
= 35 pF
8.0
12.0
ns
t
CH
Global clock high time
5.0
6.0
ns
t
CL
Global clock low time
5.0
6.0
ns
t
ASU
Array clock setup time
4.0
5.0
ns
t
AH
Array clock hold time
4.0
5.0
ns
t
ACO1
Array clock to output delay
C
L
= 35 pF
15.0
20.0
ns
t
ACH
Array clock high time
6.0
8.0
ns
t
ACL
Array clock low time
6.0
8.0
ns
t
ODH
Output data hold time after clock
C
L
= 35 pF
1.0
1.0
ns
t
CNT
Minimum global clock period
13.0
16.0
ns
f
CNT
Maximum internal global clock frequency
76.9
62.5
MHz
t
ACNT
Minimum array clock period
13.0
16.0
ns
f
ACNT
Maximum internal array clock frequency
76.9
62.5
MHz
Symbol
Speed: -20
Speed: -15
7K tbl 06C3
External Timing Parameters
AC Electrical Specifications cont.
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