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參數(shù)資料
| 型號： | CL7160SQC160-6 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復雜可編程邏輯器件 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CL7160SQC160-6 |
CL7160E and CL7160S Laser Processed Logic Devices
Page 10
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
iN
Input pad and buffer delay
0.2
0.2
0.3
ns
t
IO
I/O input pad and buffer delay
0.2
0.2
0.3
ns
t
FIN
Fast input delay
2.2
2.6
3.2
ns
t
SEXP
Shared expander delay
3.1
3.6
4.3
ns
t
PEXP
Parallel expander delay
0.9
1.0
1.3
ns
t
LAD
Logic array delay
2.6
2.8
3.4
ns
t
LAC
Logic control array delay
2.5
2.8
3.4
ns
t
IOE
Internal output enable delay
0.7
0.7
0.9
ns
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer and pad delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer enable delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
t
XZ
Output buffer disable delay
C
L
= 5 pF
[3]
4.0
4.0
4.0
ns
t
SU
Register setup time
0.8
1.0
1.2
ns
t
H
Register hold time
1.7
1.6
2.0
ns
t
FSU
Register setup time of fast input
1.9
1.9
2.2
ns
t
FH
Register hold time of fast input
0.6
0.6
0.8
ns
t
RD
Register delay
1.2
1.3
1.6
ns
t
COMB
Combinatorial delay
0.9
1.0
1.3
ns
t
IC
Array clock delay
2.7
2.9
3.5
ns
t
EN
Register enable time
2.6
2.8
3.4
ns
t
GLOB
Global control delay
1.6
2.0
2.4
ns
t
PRE
Register preset time
2.0
2.4
3.0
ns
t
CLR
Register clear time
2.0
2.4
3.0
ns
t
LIA
LIA delay
1.1
1.6
2.0
ns
t
OD1
t
OD2
Speed: -5
Speed: -6
Symbol
Speed: -7
t
ZX1
t
ZX2
t
OD3
t
ZX3
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
4.0
5.2
4.0
5.4
9.0
4.5
0.7
0.2
ns
0.9
1.0
ns
0.4
0.5
4.5
ns
4.0
ns
5.5
9.0
7K tbl 07C1
ns
ns
4.5
9.0
AC Electrical Specifications cont.
Internal Timing Parameters
[4]
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