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參數(shù)資料
| 型號(hào)： | CL7160EQI100-15 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CL7160EQI100-15 |
CL7160E and CL7160S Laser Processed Logic Devices
Page 4
Pin Name
84 pin PLCC
100 pin TQFP
100 pin PQFP
160 pin PQFP
INPUT/GCLK1
83
87
89
139
INPUT/GCLRn
1
89
91
141
INPUT/OE1
84
88
90
140
INPUT/OE2/GCLK2
2
90
92
142
TDI
14
4
6
9
TMS
23
15
17
22
TCK
62
62
64
99
TDO
71
73
75
112
GND
7, 19, 32, 42, 47, 59,
72, 82
38, 86, 11, 26, 43, 59,
74, 95
13, 28, 40, 45, 61, 76,
88, 97
17, 42, 60, 66, 95, 113,
138, 148
VCCINT
3, 43
39, 91
41, 93
61, 143
VCCIO
13, 26, 38, 53, 66, 78
3, 18, 34, 51, 66, 82
5, 20, 36, 53, 68, 84
8, 26, 55, 79, 104, 133
NC (No Connect)
6, 39, 46, 79
-
-
1, 2, 3, 4, 5, 6, 34, 35,
36, 37, 38, 39, 40, 45,
46, 47, 74, 75, 76, 81,
82, 83, 84, 85, 86, 87,
115, 116, 117, 118,
119, 120, 124, 125,
126, 127, 154, 155,
156, 157
Total user I/O pins
60
80
80
100
7160 tbl 01
Macrocell Diagram
Pin Configuration
Global
Clocks
Global
Clear
Local Array
36 Signals
from LIA
16 Expander
Product Terms
Shared Logic
Expanders
Product
Term
Select
Matrix
Parallel Logic
Expanders
Clear
Select
VCC
Clock/
Enable
Select
Register
Bypass
Fast Input
Select
Configurable
Register
to LIA
to I/O
Control
Block
from
I/O pin
PRN
ENA
CLRN
Q
D
2
7K drw 01
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