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參數(shù)資料
| 型號： | CL7160EQC160-15 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CL7160EQC160-15 |
CL7160E and CL7160S Laser Processed Logic Devices
Page 11
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
iN
Input pad and buffer delay
0.5
0.5
2.0
ns
t
IO
I/O input pad and buffer delay
0.5
0.5
2.0
ns
t
FIN
Fast input delay
1.0
1.0
1.0
ns
t
SEXP
Shared expander delay
5.0
5.0
7.0
ns
t
PEXP
Parallel expander delay
0.8
0.8
1.0
ns
t
LAD
Logic array delay
5.0
5.0
5.0
ns
t
LAC
Logic control array delay
5.0
5.0
5.0
ns
t
IOE
Internal output enable delay
2.0
2.0
2.0
ns
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer and pad delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer enable delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
t
XZ
Output buffer disable delay
C
L
= 5 pF
[3]
5.0
5.0
6.0
ns
t
SU
Register setup time
2.0
2.0
4.0
ns
t
H
Register hold time
3.0
3.0
4.0
ns
t
FSU
Register setup time of fast input
3.0
3.0
2.0
ns
t
FH
Register hold time of fast input
0.5
0.5
2.0
ns
t
RD
Register delay
2.0
2.0
1.0
ns
t
COMB
Combinatorial delay
2.0
2.0
1.0
ns
t
IC
Array clock delay
5.0
5.0
5.0
ns
t
EN
Register enable time
5.0
5.0
5.0
ns
t
GLOB
Global control delay
1.0
1.0
0.0
ns
t
PRE
Register preset time
3.0
3.0
3.0
ns
t
CLR
Register clear time
3.0
3.0
3.0
ns
t
LIA
LIA delay
1.0
1.0
1.0
ns
5.5
9.0
10.0
5.5
7K tbl 07C2
ns
ns
3.0
7.0
ns
6.0
ns
7.0
2.0
1.5
ns
2.0
4.0
ns
1.5
9.0
5.5
5.0
5.5
5.0
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
C
L
= 35 pF
t
ZX3
C
L
= 35 pF
C
L
= 35 pF
t
ZX1
t
ZX2
t
OD3
Speed: -10P
Speed: -10
Symbol
Speed: -12
t
OD1
t
OD2
AC Electrical Specifications cont.
Internal Timing Parameters
[4]
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