參數(shù)資料
型號(hào): CL7160EQC160-12
英文描述: Laser-Programmable Complex PLD
中文描述: 激光可編程復(fù)雜可編程邏輯器件
文件頁(yè)數(shù): 7/14頁(yè)
文件大?。?/td> 177K
代理商: CL7160EQC160-12
CL7160E and CL7160S Laser Processed Logic Devices
Page 7
AC Electrical Specifications
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
PD1
Input to non-registered output
C
L
= 35 pF
5.0
6.0
7.5
ns
t
PD2
I/O input to non-registered output
C
L
= 35 pF
5.0
6.0
7.5
ns
t
SU
Global clock setup time
2.9
3.4
4.2
ns
t
H
Global clock hold time
0.0
0.0
0.0
ns
t
FSU
Global clock setup time of fast input
2.5
2.5
3.0
ns
t
FH
Global clock hold time of fast input
0.0
0.0
0.0
ns
t
CO1
Global clock to output delay
C
L
= 35 pF
3.2
3.9
4.8
ns
t
CH
Global clock high time
2.0
3.0
3.0
ns
t
CL
Global clock low time
2.0
3.0
3.0
ns
t
ASU
Array clock setup time
0.7
0.9
1.1
ns
t
AH
Array clock hold time
1.8
1.7
2.1
ns
t
ACO1
Array clock to output delay
C
L
= 35 pF
5.4
6.4
7.9
ns
t
ACH
Array clock high time
2.5
3.0
3.0
ns
t
ACL
Array clock low time
2.5
3.0
3.0
ns
t
ODH
Output data hold time after clock
C
L
= 35 pF
1.0
1.0
1.0
ns
t
CNT
Minimum global clock period
5.7
6.7
8.2
ns
f
CNT
Max. internal global clock frequency
175.4
149.3
122.0
MHz
t
ACNT
Minimum array clock period
5.5
6.7
8.2
ns
f
ACNT
Max. internal array clock frequency
175.4
149.3
122.0
MHz
7K tbl 06C1
Symbol
Speed: -7
Speed: -5
Speed: -6
I/O Element Timing Parameters
[4]
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