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參數(shù)資料
| 型號： | CL7160ELC84-12 |
| 英文描述： | Laser-Programmable Complex PLD |
| 中文描述： | 激光可編程復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CL7160ELC84-12 |
CL7160E and CL7160S Laser Processed Logic Devices
Page 3
Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 to 16 I/O Pins
6 to 16 I/O Pins
6 to 16 I/O Pins
6 to 16 I/O Pins
6 to 16 I/O Pins
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
Block A
Macrocells
1 - 16
Block C
Macrocells
33 - 48
Block E
Macrocells
65 - 80
Block B
Macrocells
17 - 32
Block D
Macrocells
49 - 64
6 Output Enables
6 Output Enables
6 to 16
6 to 16
6 to 16
16
36
6
6 to 16
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36
6
6 to 16
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6
6 to 16 I/O Pins
I/O
Control
Block
Block I
Macrocells
129 - 144
6 to 16
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36
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36
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6
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6 to 16
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6
6 to 16 I/O Pins
I/O
Control
Block
Block F
Macrocells
81 - 96
6 to 16
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36
6 to 16
6 to 16
6
16
6 to 16 I/O PIns
I/O
Control
Block
Block J
Macrocells
145 - 160
6 to 16
36
6 to 16
6 to 16
6 to 16 I/O Pins
I/O
Control
Block
Block G
Macrocells
97 - 112
6 to 16
6 to 16
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36
6
6 to 16 I/O Pins
I/O
Control
Block
Block H
Macrocells
113 - 128
6 to 16
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36
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6
L
7160 drw 01
u
AN-12: CL7000 LPLD Timing and Function Compatability.
This document shows how a seamless conversion from CPLD
to ASIC can be achieve with no additional engineering with
Clear Logic.
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