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參數(shù)資料
| 型號： | CL7128EQC100-10 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 107K |
| 代理商： | CL7128EQC100-10 |
CL7128A and CL7128AE Laser Processed Logic Devices
Page 72
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
iN
Input pad and buffer delay
0.3
0.3
0.3
ns
t
IO
I/O input pad and buffer delay
0.3
0.3
0.3
ns
t
FIN
Fast input delay
2.6
2.6
2.4
ns
t
SEXP
Shared expander delay
1.9
2.4
2.8
ns
t
PEXP
Parallel expander delay
0.6
0.6
0.5
ns
t
LAD
Logic array delay
1.9
2.5
2.5
ns
t
LAC
Logic control array delay
1.8
2.3
2.5
ns
t
IOE
Internal output enable delay
0.0
0.0
0.2
ns
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer and pad delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer and pad delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 5.0 V
Output buffer enable delay
Slow slew rate = off, V
CCIO
= 3.3 V
Output buffer enable delay
Slow slew rate = on,
V
CCIO
= 5.0 V or 3.3 V
t
XZ
Output buffer disable delay
C
L
= 5 pF
[3]
4.0
4.0
4.0
ns
t
SU
Register setup time
1.4
0.8
1.0
ns
t
H
Register hold time
0.8
1.0
1.7
ns
t
FSU
Register setup time of fast input
0.9
0.8
1.2
ns
t
FH
Register hold time of fast input
1.6
1.7
1.3
ns
t
RD
Register delay
1.2
1.4
1.6
ns
t
COMB
Combinatorial delay
1.3
1.0
1.6
ns
t
IC
Array clock delay
1.9
2.3
2.7
ns
t
EN
Register enable time
1.8
2.3
2.5
ns
t
GLOB
Global control delay
1.0
0.9
1.1
ns
t
PRE
Register preset time
2.3
2.6
2.3
ns
t
CLR
Register clear time
2.3
2.6
2.3
ns
t
LIA
LIA delay
0.7
0.8
1.3
ns
Speed: -4
Speed: -5
Speed: -6
Symbol
t
OD1
C
L
= 35 pF
0.3
0.4
0.3
ns
t
OD2
C
L
= 35 pF
0.8
0.9
0.8
ns
t
OD3
C
L
= 35 pF
5.3
5.4
5.3
ns
t
ZX1
C
L
= 35 pF
4.0
4.0
4.0
ns
t
ZX2
C
L
= 35 pF
4.5
4.5
9.0
9.0
t
ZX3
C
L
= 35 pF
9.0
ns
7KA tbl 07A1
4.5
ns
AC Electrical Specifications cont.
Internal T iming Parameters
[4]
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