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參數(shù)資料
| 型號： | CL1208H |
| 英文描述： | CL1208H 10Bit 10MSPS ADC|Data Sheet |
| 中文描述： | CL1208H 10位高達10MSPS模數(shù)轉換器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 159K |
| 代理商： | CL1208H |
CL1208H
10BIT 10MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL
DESCRIPTION
1.
CL1208H
comprising a 4-bit flash ADC, three 3-bit flash
ADC and three multiplying DAC. The N-bit
flash
ADC
is
composed
comparators, and multiplying DAC is composed
of 2*(N+2) capacitors and two fully-differential
amplifier.
is
a
four
step
A/D
Converter
of
2
(n-1)
latching
2. CL1208H operates as follows. During the first
"L" cycle of external clock the analog input data
is tracked and sampled, and the input is held
from the rising edge of the external clock, which
is fed to the first 4-bit flash ADC, and the first
multiplying DAC. Multiplying DAC reconstructs
a voltage corresponding to the first 4-bit ADC's
output, and finally amplifies a residue voltage by
2
3
. The second 3-bit flash ADC, and MDAC are
worked as same manner, finally amplifiers a
residue voltage, which is the difference between
first MDAC's output and reconstructed voltage by
2
2
. The third 3-bit flash ADC, and MDAC are
worked
as
previous
stages.
residue voltage at the third multiplying DAC is
fed to the last 3-bit flash ADC decides final
3-bit digital digital code.
Finally
amplified
3. CL1208H has the error correction scheme, which
handles the output from mismatch in the first,
second, third and fourth flash ADC.
MAIN BLOCK DESCRIPTION
1. SAH
SAH(track and hold) is the circuit that samples
the analog input signal and hold that value until
next sample-time. It is good as small as its
different value between analog input signal and
output signal. SAH amp gain must be higher
than 66dB at least for less than 1/2LSB of SAH
error voltage at 10bit ADC and its conversion
frequency is 20MHz, its settling-time must be
shorten than 18ns. This SAH is consist of fully
differential op amp, switching tr. and sampling
capacitor.
The
sampling
non-overlapping
clocks(Q1,Q2)
capacitor value is 1.2pF. SAH uses independent
bias to protect interruption of any other circuit.
SAH amp is designed that open-loop dc gain is
higher than 70dB, phase margin is higher than
60degree. Its input block is designed to be the
rail-to-rail
architecture
different pair.
clock
and
are
sampling
using
complementary
2. FLASH
The 4-bit flash converter compare analog signal
(SAH output) with reference voltage, and that
result transfer to MDAC and digital correction
logic
block.
It
is
realized
comparators of 15EA. Considering self-offset,
dynamic feed through error, it should distinguish
40mV at least. First, the comparators charge the
reference
voltage
at
before transferred SAH output. Q2 works this
process
and
Q1
discharges
capacitance. That is, the comparators compare
relative different values dual input voltage with
dual reference voltage. Its output during Q1
operation is stored at the pre-latch block by
Q1P.
fully
differential
the
sampling
capacitors
this
sampling
3. MDAC
MDAC is the most important block at this
ADC and it decides the characteristics. MDAC
is consist of amp1,amp2, selection logic and
capacitor array(c_array). C_array's compositions
are the capacitors to charge the analog input and
and the reference voltage, Switches to control
the path. Selection logic controls the c_array
internal
switches.
If
output are all low, the switches of tsw1 are off,
the switches of tsw2 are all on. Therefore the
capacitors of c_array charge analog input values
holded at SAH. If Q2 is high, it is reversed and
final MDAC output voltage is described the
following equation.
Q1
is
high,
selection's
Vout = (AIN - Vref)*8-Vref/2
AIN=AINT-2.5V
6 / 12
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