參數(shù)資料
型號: CL-SH8665
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: Integrated ATA Drive microcontroller(集成ATA驅(qū)動微控制器)
中文描述: 32-BIT, MROM, RISC MICROCONTROLLER
文件頁數(shù): 2/4頁
文件大?。?/td> 161K
代理商: CL-SH8665
CL-SH8665
Integrated ATA Drive Electronics
FEATURES
(cont.)
ATA Disk Controller (CL-SH7656)
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Ultra DMA support (33.3 Mbytes/sec.)
Direct buffer access by CPU
Buffer bandwidth
— 64 Mbytes/sec. with EDO DRAM and 40-MHz SYSCLK
8-bit NRZ disk data rate — 260 Mbits/sec.
maximum
Advanced ECC capabilities
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Read Channel
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User data rate from 47 to 245 Mbits/sec.
Digitally controlled VGA (variable gain amplifier)
Ten-tap adaptive digital FIR (finite impulse
response) equalization filter
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Fourth-order analog LPF (low-pass filter)
6-bit flash ADC (analog-to-digital converter)
Rate 16/17 d=0 RLL encoder/decoder
Enhanced PR4 partial response sequence
detector
Thermal asperity detection and correction capa-
bility for MR heads
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General
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Customer-defined control logic
On-chip oscillator and frequency synthesizer
Power management
— Three system power modes (Run, Idle, and Sleep), plus
clock disabling of idle subsystems
3.3-volt, 0.35-micron design
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manage servo and spindle control, as well as disk
controller and other drive functions.
The Thumb
instructions to be executed within the 32-bit proces-
sor core, reducing the firmware code size with no
penalty in performance. For critical functions, such
as servo processing or interrupt handling, 32-bit
instructions can be employed. A high-speed 16-bit
external bus is used for instruction fetch from flash
memory. Data memory can be accessed through
the internal SRAM or by using a portion of the buffer
memory with direct processor access through the
disk controller.
technology from ARM
allows 16-bit
The hard disk controller logic (CL-SH7656 core)
offers full hardware support of the ID-less architec-
ture, including automatic sector pulse generation,
logical sector mapping and on-track defect manage-
ment. Buffer bandwidth using EDO DRAM of up to
64 Mbytes/sec. can sustain host data rates of 33.3
Mbytes/sec. in Ultra DMA mode 2 and disk data
rates up to 260 Mbits/sec. (for the controller). The
advanced ECC logic provides five-byte error correc-
tion and can correct a single-burst error of 113 bits
or a double-burst error of 49 bits on-the-fly. In addi-
tion, higher ECC correction power can be achieved
with off-line firmware correction and erasure pointer
support.
The read channel logic (CL-SH3360 core) is a sam-
pled amplitude digital read/write channel that pro-
vides a highly flexible, state-of-the-art, synchronous
read path for high-density magnetic disk drives. In
addition, this block has a programmable architec-
ture and calibration feature that allows the channel
parameters to be tuned to characteristics of each
drive, head, and zone. High disk data rates — up to
245 Mbits/sec. (for the channel) — and erasure
pointers are supported.
As shown in the system block diagram on
page 1
,
the CL-SH8665, external flash memory, external
buffer memory, a preamplifier, and the power drivers
comprise the bulk of the drive electronics required
for an ATA disk drive.
An on-chip oscillator and frequency synthesizer pro-
vide all clock frequencies required by the processor,
peripheral, and disk controller subsystems. Sophis-
ticated power management can be configured for
three system power modes, plus automatic clock
disabling of idle subsystems delivers maximum
power savings.
The CL-SH8665 is designed in a 3.3-volt, 0.35-
micron process with 5-volt-tolerant I/Os. The device
is available in a 208-pin package.
OVERVIEW
(cont.)
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