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參數(shù)資料
| 型號： | CL-CS3712 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Integrated AVI/ATAPI DVD Drive Manager |
| 中文描述： | 綜合阿維/ DVD驅(qū)動器管理器的ATAPI |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 728K |
| 代理商： | CL-CS3712 |
C
ONFIDENTIAL
DS588PP1 -
rev
0.4 April 11, 2002
Copyright
2002 Cirrus Logic Inc.
Functional Decriptions
P
RELIMINARY
D
RAFT
www.cirrus.com
5
The CL-CS3712 data channel architecture minimizes analog signal processing and
migrates all feasible functionality to real-time digital signal processing blocks. The
analog blocks are:
Summation Amplifier
Digitally Controlled Variable Gain Amplifier (VGA)
Analog Low Pass Filter (LPF)
Analog-to-Digital Converter (RF ADC)
The main data path digital blocks are:
Digital Equalizer
Interpolate Timing Recovery (ITR)
Sequence Detector
The data path blocks are supported by the loop control blocks: the digital automatic gain
control (DAGC), offset control, and digital asymmetry control. The digital defect detect
block allows the loops and the servo processor to coast through defects. u-Controller
accessible channel quality metrics support servo error signal gain and offset calibration.
The Attenuator and Summation block interfaces the OPU's A, B, C, and D photodetector
outputs or the RF signal to the data channel. The attenuator and offset loop keeps the
signals within the linear range of the circuitry. The channel can use either internally or
externally summed RF.
The variable gain amplifier (VGA) is part of the automatic gain control (AGC) loop. This
amplifier's gain is exponentially proportional to its gain control. The analog low pass filter
is designed to limit noise and serve as an anti-aliasing filter.
The CL-CS3712 contains a high speed analog to digtial convertor that allows the
majority of the signal processing to be performed in the digital domain. The sampling
frequency is fixed and can be Fsynth/2 or Fsynth/4. This allows for a wide range of
allowable input data rates.
The digital equalizer is a 5 tap finite impulse response filter. It's coefficients change
automatically as the data rate changes. The envelope detector is used to generate error
signals for the offset and AGC loops. The defect detection is also performed here. The
digital offset loop keeps the read signal's baseline at the ADC's range center. The AGC
also keeps the signal's amplitude within the ADC's range. These loops are digital with
the exception of the digital to analog convertors (DACs), ADC, an adder, and a VGA.
The CL-CS3712 data channel performs data separation via the ITR. This all digital
implementation of a phase locked-loop (PLL) makes for consistent chip to chip
performance. It also allows for wide capture ranges. This decreases the speed of seeks
in constant linear velocity (CLV) mode. It has been designed handle the rate changes
inherent in constant angular velocity (CAV) mode automatically. Asymmetry
compensation is performed at the ITR input.
The CL-CS3712
contains a maximum likelihood sequence detector especially designed
for low resolution DVD signals. This sequence detector achieves substantial signal
processing gain over a slicer detector.
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