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參數(shù)資料
| 型號： | CH7301A-T-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7301 DVI Output Device |
| 中文描述： | 昆泰CH7301 DVI輸出設(shè)備 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 485K |
| 代理商： | CH7301A-T-B |
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201-0000-036 Rev 1.1, 3/20/2000
7
CHRONTEL
Input Interface
CH7301A
Two distinct methods of transferring data to the CH7301 are described. They are:
Multiplexed data, clock input at 1X pixel rate
Multiplexed data, clock input at 2X pixel rate
For the multiplexed data, clock at 1X pixel rate the data applied to the CH7301 is latched with both edges of
the clock (also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate the data
applied to the CH7301 is latched with one edge of the clock. The polarity of the pixel clock can be reversed
under IIC control.
Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform
represents the input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK*
waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method.
Figure 4: Interface Timing
1
D[11:0], H, V DE times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges.
Table 3: Interface Timing
Symbol
Parameter
V
OH
Output high level of interface signals
V
OL
Output Low level of interface signals
t1
1
D[11:0], H, V & DE to XCLK = XCLK* Delay (setup
time)
t2
1
XCLK = XCLK* to D[11:0], H, V & DE Delay (hold time)
DVDDV Digital I/O Supply Voltage
Min
Max
Unit
V
DVDDV - 0.2
DVDDV + 0.2
-0.2
0.2
V
TBD
nS
TBD
nS
1.1 – 5%
3.3 + 5%
V
D[11:0]
XCLK/
XCLK*
H
V
DE
64 P-OUT
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
t1
t2
t2
t1
1 VGA Line
XCLK/
XCLK*
V
OH
V
OL
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