
CE71SeriesEmeddedAray
0.25μmCMOS Technology
Features
0.18μmL
eff
(0.24μmdrawn)
Propagation deay of 61 ps
Separatecoreand I/O supply voltages
Mixed-signal macros–A/D and D/A converters
I/Os: 2.5V, 3.3V, 5V tolerant
Corepower supply voltage 2.5V, 1.8V, 1.5V
Junction temperature -40oC~125oC
High performanceand special I/Os–PCML, LVDS, PCI,
SSTL, GTL+, AGP USB
Analog and digital PLLs
Packaging options: QFP HQFP BGA, TBGA
Support for major third-party EDA tools
t
Embedded
Hard
Macro
SoFixed
SoFixed
Clock Tree
Clk
PCI
5V Tol.
3V
PCML
Descripion
Fujitsus CE71 is a series of high-performance 0.18μmL
eff
CMOS embedded arrays that includefull support of diffused
high-speed RAMs, ROMs, mxed-signal macros, and a
variety of other embedded functions.
t
TheCE71 series offers density and performancesimlar to
thoseof standard cels, yet provides thetime-to-market
advantageof gatearrays. TheCE71 series devices include
44μm 66μm or 88μmpad pitch for a cost-effective
solution for both pad-limted and core-limted designs.
With a nomnal 1.5V to 2.5V coreoperation and with 2.5V
and 3.3V/5V tolerant I/Os, theCE71 series features a very
low-power consumption of 0.06μW/gate/MHz. Potential
applications for theCE71 series includecomputing, graphics
communications networking, wireess and consumer designs.
J-Series with 66μm Stagger Pad Pitch and Wire Bonding
Frame
CE71J1
CE71J2
CE71J3
CE71J4
CE71J5
CE71J6
CE71J7
CE71J8
CE71J9
CE71JA
CE71JB
CE71JC
CE71JD
CE71JE
CE71JF
CE71JG
Total Gates
216K
312K
488K
703K
911K
1,098K
1,302K
1,524K
2.020K
2,586K
3,055K
3,564K
4,113K
5,114K
6,698K
8,096K
Total Pads
192
224
272
320
360
392
424
456
520
584
632
680
728
808
920
1,008
Signals
152
152
178
206
264
304
360
360
360
472
472
506
506
506
506
506
K-Series with 88μm Inline Pad Pitch and Wire Bonding
Frame
CE71K1
CE71K2
CE71K3
CE71K4
CE71K5
CE71K6
CE71K7
CE71K8
Total Gates
167K
237K
348K
524K
734K
963K
1,110K
1,559K
Total Pads
100
120
144
176
208
240
256
304
Signals
88
102
126
152
178
206
220
264