參數(shù)資料
型號(hào): CDR01BP270BJW4
廠商: KEMET Corporation
英文描述: CERAMIC CHIP CAPACITORS
中文描述: 陶瓷芯片電容器
文件頁(yè)數(shù): 19/30頁(yè)
文件大?。?/td> 2058K
代理商: CDR01BP270BJW4
KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
CERAMIC CAPACITOR ARRAY
Four individual capacitors inside
one 1206 monolithic structure
Saves board and inventory space
One placement instead of four - less costly
Easier to handle and solder than 4 smaller chips
Tape and reel per EIA 481-1
RoHS Compliant
FEATURES
W
BW
P/2
Ref
P
L
CL
BW1
T
CAPACITOR OUTLINE DRAWING
TABLE 1
EIA DIMENSIONS – MILLIMETERS (INCHES)
1632
3.2 (0.126)
±
0.2 (0.008)
1.6 (.063)
±
0.2 (.008)
0.7 - 1.35
(0.027 - 0.053)
0.40 (0.016)
±
0.2 (0.008)
0.1 - 0.5
(0.004 - 0.020)
Size
Code
Length
L
Width
W
Thickness
T (max.)
Bandwidth
BW
Bandwidth
BW1
0.8 (0.031)
±
0.1 (0.004)
Pitch
P
Notes:
1. Metric is controlling - English for reference only.
2. Pitch (P) tolerances are non-cumulative along the package.
3. Thickness (T) depends on capacitance.
END METALLIZATION
C-Standard
(Tin-plated nickel barrier)
FAILURE RATE LEVEL
A- Not Applicable
Expressed in Picofarads (pF)
First two digits represent significant figures.
Third digit specifies number of zeros. (Use 9
for 1.0 thru 9.9pF (Example: 2.2pF = 229
CAPACITANCE TOLERANCE
K –
±
10%: M –
±
20% Standard Tolerances
Contact factory for any special requirements.
CERAMIC
EIA SIZE CODE
Ceramic chip array
SPECIFICATION
C - Standard
CAPACITANCE CODE
VOLTAGE
5 = 50v; 3 = 25v; 4 = 16v; 8=10v
C
1632
C
103
K
5
R
C
A
TEMPERATURE CHARACTERISTIC
Designated by Capacitance
Change Over Temperature Range
G – C0G (NP0) (
±
30 PPM/
°
C)
R – X7R (
±
15%)
CERAMIC ARRAY ORDERING INFORMATION
8
5
C
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