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參數(shù)資料
| 型號： | CDP6872H |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Low Power Crystal Oscillator |
| 中文描述： | 10 MHz, OTHER CLOCK GENERATOR, UUC8 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 101K |
| 代理商： | CDP6872H |
4
Test Circuits
FIGURE 1.
In production the CDP6872 is tested with a 32kHz and a
1MHz crystal. However for characterization purposes data
was taken using a sinewave generator as the frequency
determining element, as shown in Figure 1. The 1V
P-P
input
is a smaller amplitude than what a typical crystal would gen-
erate so the transitions are slower. In general the Generator
data will show a “worst case” number for I
DD
, duty cycle, and
rise/fall time. The Generator test method is useful for testing
a variety of frequencies quickly and provides curves which
can be used for understanding performance trends. Data for
the CDP6872 using crystals has also been taken. This data
has been overlaid onto the generator data to provide a refer-
ence for comparison.
Theory of Operation
The CDP6872 is a Pierce Oscillator optimized for low power
consumption, requiring no external components except for a
bypass capacitor and a Parallel Mode Crystal. The Simpli-
fied Block Diagram shows the Crystal attached to pins 2 and
3, the Oscillator input and output. The crystal drive circuitry
is detailed showing the simple CMOS inverter stage and the
P-channel device being used as biasing resistor R
F
. The
inverter will operate mostly in its linear region increasing the
amplitude of the oscillation until limited by its transconduc-
tance and voltage rails, V
DD
and V
RN
. The inverter is self
biasing using R
F
to center the oscillating waveform at the
input threshold. Do not interfere with this bias function with
external loads or excessive leakage on pin 2. Nominal value
for R
F
is 17M
in the lowest frequency range to 7M
in the
highest frequency range.
The CDP6872 optimizes its power for 4 frequency ranges
selected by digital inputs Freq1 and Freq2 as shown in the
Block Diagram. Internal pull up resistors (constant current
0.4
μ
A) on Enable, Freq1 and Freq2 allow the user simply to
leave one or all digital inputs not connected for a corre-
sponding “1” state. All digital inputs may be left open for
10kHz to 100kHz operation.
A current source develops 4 selectable reference voltages
through series resistors. The selected voltage, V
RN
, is buff-
ered and used as the negative supply rail for the oscillator
1
2
3
4
8
7
6
5
CDP6872
V
OUT
C
L
+5V
18pF
0.1
μ
F
1000pF
50
ENABLE
FREQ 2
FREQ 1
1V
P-P
CDP6872
section of the circuit. The use of a current source in the refer-
ence string allows for wide supply variation with minimal
effect on performance. The reduced operating voltage of the
oscillator section reduces power consumption and limits
transconductance and bandwidth to the frequency range
selected. For frequencies at the edge of a range, the higher
range may provide better performance.
The OSC OUT waveform on pin 3 is squared up through a
series of inverters to the output drive stage. The Enable
function is implemented with a NAND gate in the inverter
string, gating the signal to the level shifter and output stage.
Also during Disable the output is set to a high impedance
state useful for minimizing power during standby and when
multiple oscillators are OR'd to a single node.
Design Considerations
The low power CMOS transistors are designed to consume
power mostly during transitions. Keeping these transitions
short requires a good decoupling capacitor as close as pos-
sible to the supply pins 1 and 4. A ceramic 0.1
μ
F is recom-
mended. Additional supply decoupling on the circuit board
with 1
μ
F to 10
μ
F will further reduce overshoot, ringing and
power consumption. The CDP6872, when compared to a
crystal and inverter alone, will speed clock transition times,
reducing power consumption of all CMOS circuitry run from
that clock.
Power consumption may be further reduced by minimizing
the capacitance on moving nodes. The majority of the power
will be used in the output stage driving the load. Minimizing
the load and parasitic capacitance on the output, pin 5, will
play the major role in minimizing supply current. A secondary
source of wasted supply current is parasitic or crystal load
capacitance on pins 2 and 3. The CDP6872 is designed to
work with most available crystals in its frequency range with
no external components required. Two 15pF capacitors are
internally switched onto crystal pins 2 and 3 to compensate
the oscillator in the 10kHz to 100kHz frequency range.
The supply current of the CDP6872 may be approximately
calculated from the equation:
I
DD
= I
DD
(Disabled) + V
DD
×
F
OSC
×
C
L
where:
I
DD
= Total supply current
V
DD
= Total voltage from V
DD
(pin1) to V
SS
(pin4)
F
OSC
= Frequency of Oscillation
C
L
= Output (pin5) load capacitance
Example #1:
V
DD
= 5V, F
OSC
= 100kHz, C
L
= 30pF
I
DD
(Disabled) = 4.5
μ
A (Figure 10)
I
DD
= 4.5
μ
A + (5V)(100kHz)(30pF) = 19.5
μ
A
Measured I
DD
= 20.3
μ
A
Example #2:
V
DD
= 5V, F
OSC
= 5MHz, C
L
= 30pF
I
DD
(Disabled) = 75
μ
A (Figure 9)
I
DD
= 75
μ
A + (5V)(5MHz)(30pF) = 825
μ
A
Measured I
DD
= 809
μ
A
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