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參數(shù)資料
| 型號： | CDP1883C |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 7-Bit Latch and Decoder Memory Interfaces(CMOS 7位鎖存和解碼存儲器接口) |
| 中文描述： | 的CMOS 7位鎖存器和解碼器存儲器接口的CMOS（7位鎖存和解碼存儲器接口） |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 32K |
| 代理商： | CDP1883C |
4-133
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ISO9000
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
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and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
CLOCK to Address
t
CLA
5
-
100
175
-
100
175
ns
10
-
65
125
-
-
-
ns
Memory Address to Chip Select
t
MACS
5
-
100
175
-
100
175
ns
10
-
75
125
-
-
-
ns
Memory Address to Address
t
MAA
5
-
80
125
-
80
125
ns
10
-
40
60
-
-
-
ns
NOTES:
1. Typical values are for T
A
= 25
o
C.
2. Maximum limits of minimum characteristics are the values above which all devices function.
FIGURE 1. CDP1883 TIMING WAVEFORMS
Dynamic Electrical Specifications
T
A
= -40
o
C to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF.
See Figure 1
(Continued)
PARAMETER
V
DD
(V)
CDP1883
CDP1883C
UNITS
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
VALID CHIP ENABLE
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
(B) MEMORY ADDRESS SETUP AND HOLD TIME
t
CECS
t
CECS
t
CLMA
t
MACL
t
CLCL
t
CLCS
t
CLA
A8 - A12
CS0, CS1, CS2, CS3
CLOCK
MA0 - MA5
CS0, CS1, CS2, CS3
CE
t
MACS
t
MACS
t
MAA
t
MAA
CDP1883, CDP1883C
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| CDP1883E | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 7-Bit Latch and Decoder Memory Interfaces |
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