- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379858 > CDP1883 (Intersil Corporation) CMOS 7-Bit Latch and Decoder Memory Interfaces(CMOS 7位鎖存和解碼存儲器接口) PDF資料下載
參數(shù)資料
| 型號： | CDP1883 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 7-Bit Latch and Decoder Memory Interfaces(CMOS 7位鎖存和解碼存儲器接口) |
| 中文描述： | 的CMOS 7位鎖存器和解碼器存儲器接口的CMOS（7位鎖存和解碼存儲器接口） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 32K |
| 代理商： | CDP1883 |
4-132
Signal Descriptions/Pin Functions
CLOCK:
Latch Input Control - a high on the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high-to-low transition of the clock input. This
pin is connected to TPA in CDP1800-series systems and tied
to V
DD
for other applications.
MA0 - MA4:
Address inputs to the high-byte address
latches.
MA5 - MA6:
High byte address inputs decoded to produce
chip selects CS0 - CS3.
CE:
CHIP ENABLE input - A low on this pin will enable the
chip select decoder. A high on this pin forces CS0, CS1,
CS2, and CS3 outputs to a high (false) state.
A8 - A12:
Latched high-byte address outputs.
CS0 - CS3:
One of four latched and decoded Chip Select
outputs.
V
DD
, V
SS
:
Power and ground pins, respectively.
Application Information
The CDP1883 and CDP1883C can be interfaced, without
external components, with CDP1800-series microprocessor
systems. These microprocessors feature a multiplexed
address bus and provide an address latch signal (TPA) that
is used as the clock input of the CDP1883. See Figure 2 and
Figure 3.
This signal is used to latch 7 bits of the high-order address.
The lower five high-order address inputs are latched and
held to be used with the eight lower-order address inputs to
access an 8K x 8-bit memory. The two upper high-order
address inputs are latched and decoded for use as chip
selects.
The latched address and decoding functions of the
CDP1883 and CDP1883C allow them to operate with 32K-
byte memory systems. In addition, smaller memory systems
can be configured with 4K x 8-bit or smaller memories, or a
mix of memory sizes up to 8K x 8-bit.
TRUTH TABLE
INPUTS
OUTPUTS
CE
CLK
MA5
MA6
CS0
CS1
CS2
CS3
0
1
0
0
0
1
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
X
X
Previous State
1
X
X
X
1
1
1
1
TRUTH TABLE
INPUTS
OUTPUTS
CE
CLK
MA0 - 4
A8 - A12
X
1
1
1
X
1
0
0
X
0
X
Previous State
X = Don’t Care
Dynamic Electrical Specifications
T
A
= -40
o
C to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF.
See Figure 1
PARAMETER
V
DD
(V)
CDP1883
CDP1883C
UNITS
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
Minimum Setup Time,
Memory Address to CLOCK
t
MACL
5
-
10
35
-
10
35
ns
10
-
8
25
-
-
-
ns
Minimum Hold Time,
Memory Address After CLOCK
t
CLMA
5
-
8
25
-
8
25
ns
10
-
8
25
-
-
-
ns
Minimum CLOCK Pulse Width
t
CLCL
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
PROPAGATION DELAY TIMES
Chip Enable to Chip Select
t
CECS
5
-
75
150
-
75
150
ns
10
-
45
100
-
-
-
ns
CLOCK to Chip Select
t
CLCS
5
-
100
175
-
100
175
ns
10
-
65
125
-
-
-
ns
CDP1883, CDP1883C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1883C | CMOS 7-Bit Latch and Decoder Memory Interfaces(CMOS 7位鎖存和解碼存儲器接口) |
| CDP1883E | CMOS 7-Bit Latch and Decoder Memory Interfaces |
| CDP6872 | Low Power Crystal Oscillator |
| CDP6872E | Low Power Crystal Oscillator |
| CDP6872H | Low Power Crystal Oscillator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1883 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1883_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 7-Bit Latch and Decoder Memory Interfaces |
| CDP1883C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 7-Bit Latch and Decoder Memory Interfaces |
| CDP1883CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CDP1883CE | 制造商:Harris Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。