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參數(shù)資料
| 型號(hào)： | CDP1882D |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | CMOS 6-Bit Latch and Decoder Memory Interfaces |
| 中文描述： | 1800 SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP18 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 48K |
| 代理商： | CDP1882D |
4-4
TRUTH TABLE
INPUTS
OUTPUTS
(NOTE 1)
MWR
(NOTE 1)
MRD
CE
CLK
MA4
MA5
CS0
CS1
CS2
CS3
1
1
X
X
X
X
1
1
1
1
X
X
1
X
X
X
1
1
1
1
0
X
0
1
0
0
0
1
1
1
0
X
0
1
1
0
1
0
1
1
0
X
0
1
0
1
1
1
0
1
0
X
0
1
1
1
1
1
1
0
0
X
0
0
X
X
Previous State
X
0
0
1
0
0
0
1
1
1
X
0
0
1
1
0
1
0
1
1
X
0
0
1
0
1
1
1
0
1
X
0
0
1
1
1
1
1
1
0
X
0
0
0
X
X
Previous State
NOTE:
1. CDP1881C Only
INPUTS
OUTPUTS
CE
CLK
MA0, MA1, MA2, MA3
A8, A9, A10, A11
X
1
1
1
X
1
0
0
X
0
X
Previous State
Logic 1 = High, Logic 0 = Low, X = Don’t Care
Dynamic Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
(See Figure 1)
PARAMETER
V
DD
(V)
CDP1882
CDP1881C, CDP1882C
UNITS
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
Minimum Setup Time
t
MACL
5
-
10
35
-
10
35
ns
Memory Address to CLOCK
10
-
8
25
-
-
-
ns
Minimum Hold Time
t
CLMA
5
-
8
25
-
8
25
ns
Memory Address After CLOCK
10
-
8
25
-
-
-
ns
Minimum CLOCK Pulse Width
t
CLCL
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
CDP1881C, CDP1882, CDP1882C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1882DX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1882E | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC |
| CDP1883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS 7-Bit Latch and Decoder Memory Interfaces |
| CDP1883 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1883_1 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS 7-Bit Latch and Decoder Memory Interfaces |
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