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參數(shù)資料
| 型號(hào)： | CDP1882 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 6-Bit Latch and Decoder Memory Interfaces(CMOS ６位鎖存和解碼存儲(chǔ)器接口) |
| 中文描述： | 的CMOS 6位鎖存器和解碼器存儲(chǔ)器接口的CMOS（6位鎖存和解碼存儲(chǔ)器接口） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 48K |
| 代理商： | CDP1882 |
4-6
Signal Descriptions/Pin Functions
CLOCK:
Latch-Input Control - a high at the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high to low transition of the clock input. This
input is connected to TPA in CDP1800-series systems.
MA0 - MA3:
Address inputs to the high-byte address
latches.
MA4 - MA5:
High byte address inputs decoded to produce
chip selects CS0 - CS3.
MRD, MWR:
MEMORY READ (MRD) and MEMORY WRITE
(MWR) signal inputs on the CDP1881C. A low at either
input, when the CE pin is low, will enable the decoder chip
select outputs (CS0 - CS3).
CE:
CHIP ENABLE input - a low at the CE input of
CDP1882, CDP1882C will enable the chip select decoder. A
low at the CE input of CDP1881C, coincident with a low at
either MRD or MRW pin, will enable the chip select decoder.
A high on this pin forces CS0, CS1, CS2, and CS3 to a high
(false) state.
A8 - A11:
Latched high-byte address outputs.
CS0 - CS3:
One of four latched and decoded Chip Select
outputs.
V
DD
, V
SS
:
Power and ground pins, respectively.
Application Information
The CDP1881C, CDP1882, CDP1882C can interface
directly with the multiplexed address bus of the CDP1800-
series microprocessor family at maximum clock frequency. A
single CDP1881C or CDP1882 is capable of decoding up to
16K-bytes of memory.
The CDP1881C is provided with MRD and MWR inputs for
controlling bus contention, and is especially useful for inter-
facing with RAMs that do not have an output enable function
(OE). Figure 4 shows the CDP1881C in a minimum system
configuration which includes the CDP1833 ROM (1K x 8)
and two 2K x 8 RAMS. The CDP1881C in this example per-
forms the following functions:
1) Latch and decode high-order address bits for use as chip
selects.
2) Gate chip selects with MRD and MWR to prevent bus
contention with the CPU.
3) Latch high-order address bits A8 to A11.
A system using the CDP1882 is shown in Figure 5. The
CDP1882 performs the memory address latch and decoder
functions. Note that the RAM has an output enable (OE) pin
which eliminates the need for MRD and MWR inputs on the
latch/decoder. Instead, the MRD line is connected directly to
the RAM output enable (OE) pin.
In Figure 6 the CDP1882 is used to decode a 16K-byte ROM
system consisting of four CDM5332s.
FIGURE 4. MINIMUM 1800-SERIES USING THE CDP1881C
CDP1881C
LATCH/
DECODER
MA0 - MA5
CLK
A11
CS0
CS1
CS2
CS3
R/W
CS
CE
B
(NOTE 1)
CE
A
(NOTE 1)
A0 - A7
(2) 2K x 8
RAMS
CE
MRD
MWR
CDP1883
1K x 8
ROM
TPA
A0 - A7
MRD
CEO
TPA
MRD
MWR
CDP1800
SERIES
CPU
WAIT
CLR
A8 - A10
ADDRESS BUS
DATA BUS
NOTE: CE
A
= CE RAM NUMBER 1
CE
B
= CE RAM NUMBER 2
CDP1881C, CDP1882, CDP1882C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1882C | CMOS 6-Bit Latch and Decoder Memory Interfaces(CMOS ６位鎖存和解碼存儲(chǔ)器接口) |
| CDP1882CEX | CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1882CE | CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1882D | CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1883CE | CMOS 7-Bit Latch and Decoder Memory Interfaces |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1882 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1882C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1882CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CDP1882CDX | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CDP1882CE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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