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參數(shù)資料
| 型號(hào)： | CDP1879E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Real-Time Clock |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 100K |
| 代理商： | CDP1879E |
4-118
FIGURE 12. CDP1800 SERIES MEMORY MAPPED WRITE CYCLE TIMING WAVEFORMS
FIGURE 13. CDP1800 SERIES MEMORY MAPPED READ CYCLE TIMING WAVEFORMS
FIGURE 14. TYPICAL CDP1802 INPUT/OUTPUT MAPPED SYSTEM
LATCH HIGH-ORDER
ADDRESS FOR CS
HIGH BYTE
LOW BYTE
DATA LATCHED
VALID DATA
DATA FROM CPU
TO REAL TIME CLOCK
TPB/WR
ADDRESS
TPA
HIGH BYTE
LOW BYTE
VALID DATA
OUTPUT DRIVERS
ENABLED
DISABLED
DATA FROM
RD
ADDRESS
TPA
REAL TIME CLOCK
TO CPU
CLEAR
TPA
MRD
TPB
INTERRUPT
N0
N1
N2
CDP1802
MEMORY
CDP1879
DB0 - DB7
ADDRESS
LINES
RESET
TPA
RD
TPB/WR
INTERRUPT
A0
A1
A2
IO/MEM
XTAL
XTAL
CLOCK
OUT
V
DD
CS
CDP1879, CDP1879C-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1879CE1 | CMOS Real-Time Clock |
| CDP1881CE | CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1881C | CMOS 6-Bit Latch and Decoder Memory Interfaces(CMOS ６位鎖存和解碼存儲(chǔ)器接口) |
| CDP1882 | CMOS 6-Bit Latch and Decoder Memory Interfaces(CMOS ６位鎖存和解碼存儲(chǔ)器接口) |
| CDP1882C | CMOS 6-Bit Latch and Decoder Memory Interfaces(CMOS ６位鎖存和解碼存儲(chǔ)器接口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1881C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1881CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 6-Bit Latch and Decoder Memory Interfaces |
| CDP1881CE WAF | 制造商:Harris Corporation 功能描述: |
| CDP1881E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CDP1882 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 6-Bit Latch and Decoder Memory Interfaces |
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