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參數(shù)資料
| 型號(hào)： | CDP1874C |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Speed 8-Bit Input and Output Ports(高速8位并行I/O端口) |
| 中文描述： | 高速8位輸入和輸出端口（高速8位并行的I / O端口） |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 32K |
| 代理商： | CDP1874C |
4-78
Logic Diagrams
FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) FOR CDP1872C
FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) for CDP1874C
FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C
Dynamic Electrical Specifications
At T
A
= 25
o
C, V
DD
5V, t
R
, t
F
= 10ns, V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
, C
L
= 150pF
PARAMETER
LIMITS
UNITS
CDP1872C, CDP1874C
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
INPUT PORT (FIGURE 4)
Output Enable
t
EN
-
45
90
ns
Output Disable
t
DIS
-
45
90
ns
Clock to Data Out
t
CLO
-
45
90
ns
Clear to Output
t
CRO
-
80
160
ns
Data In to Data Out
t
DIO
-
50
85
ns
Minimum Data Setup Time
t
DSU
-
10
30
ns
Data Hold Time
t
DH
-
10
30
ns
Minimum Clock Pulse Width
t
CL
-
30
60
ns
Minimum Clear Pulse Width
t
CR
-
30
60
ns
NOTES:
1. Typical values are for T
A
= +25
o
C and V
DD
±
5%.
2. Maximum values are for T
A
= +85
o
C and V
DD
±
5%
D
C
R
Q
CS1
CS2
DI
CLOCK
CLR
DO
D
C
R
Q
CS1
CS2
DI
CLOCK
CLR
DO
D
C
R
Q
CS1
CS2
CS3
CLR
DO
DI
CDP1872C, CDP1874C, CDP1875C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1872 | High-Speed 8-Bit Input and Output Ports |
| CDP1872C | High-Speed 8-Bit Input and Output Ports |
| CDP1872CE | High-Speed 8-Bit Input and Output Ports |
| CDP1875C | High-Speed 8-Bit Input and Output Ports(高速8位并行I/O端口) |
| CDP1874CE | High-Speed 8-Bit Input and Output Ports |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1874CD | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral IC |
| CDP1874CE | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:High-Speed 8-Bit Input and Output Ports |
| CDP1874CE116 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1875C | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:High-Speed 8-Bit Input and Output Ports |
| CDP1875CD | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral IC |
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