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參數(shù)資料
| 型號： | CDP1872CE |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | High-Speed 8-Bit Input and Output Ports |
| 中文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDIP22 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 32K |
| 代理商： | CDP1872CE |
4-78
Logic Diagrams
FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) FOR CDP1872C
FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) for CDP1874C
FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C
Dynamic Electrical Specifications
At T
A
= 25
o
C, V
DD
5V, t
R
, t
F
= 10ns, V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
, C
L
= 150pF
PARAMETER
LIMITS
UNITS
CDP1872C, CDP1874C
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
INPUT PORT (FIGURE 4)
Output Enable
t
EN
-
45
90
ns
Output Disable
t
DIS
-
45
90
ns
Clock to Data Out
t
CLO
-
45
90
ns
Clear to Output
t
CRO
-
80
160
ns
Data In to Data Out
t
DIO
-
50
85
ns
Minimum Data Setup Time
t
DSU
-
10
30
ns
Data Hold Time
t
DH
-
10
30
ns
Minimum Clock Pulse Width
t
CL
-
30
60
ns
Minimum Clear Pulse Width
t
CR
-
30
60
ns
NOTES:
1. Typical values are for T
A
= +25
o
C and V
DD
±
5%.
2. Maximum values are for T
A
= +85
o
C and V
DD
±
5%
D
C
R
Q
CS1
CS2
DI
CLOCK
CLR
DO
D
C
R
Q
CS1
CS2
DI
CLOCK
CLR
DO
D
C
R
Q
CS1
CS2
CS3
CLR
DO
DI
CDP1872C, CDP1874C, CDP1875C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1875C | High-Speed 8-Bit Input and Output Ports(高速8位并行I/O端口) |
| CDP1874CE | High-Speed 8-Bit Input and Output Ports |
| CDP1875CE | High-Speed 8-Bit Input and Output Ports |
| CDP1877 | Programmable Interrupt Controller (PIC)(可編程中斷控制器) |
| CDP1877C | Programmable Interrupt Controller (PIC)(可編程中斷控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1872CE WAF | 制造商:Harris Corporation 功能描述: |
| CDP1872D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| CDP1872E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| CDP1873CD | 制造商:Harris Corporation 功能描述: |
| CDP1873CDX | 制造商:Harris Corporation 功能描述: |
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