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參數(shù)資料
| 型號： | CDP1871AD |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Keyboard Encoder |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP40 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 56K |
| 代理商： | CDP1871AD |
4-73
and read by the CPU, at which time the next key pressed in
the scanning order is detected. If the first key remains closed
after the CPU reads the data and resets the DA output, on
the low-to-high transition of TPB, an auxiliary signal (RPT) is
generated and is available to the CPU to indicate an auto-
repeat condition. The RPT output is reset high at the end of
the debounce delay after the depressed key is released.
The DEBOUNCE input provides a terminal connection for an
external user-selected RC circuit to eliminate false detection
of a keydown condition caused by keyboard noise. The oper-
ation of the DEBOUNCE circuit is shown in Figure 2 (Pin
36). When a valid keydown is detected, the on-chip active-
resistor device (R
N
) is enabled and the external capacitor
(C
X
) is discharged, providing a key closure debounce time
R
N
C
X
. This discharge is sensed by the Schmitt-trigger
inverter, which clocks the DA flip-flop (latching the DA output
low and inhibiting the scan clock). (The DA F/F is reset by
the low-to-high transition of TPB when the CS inputs are
enabled). When a valid key-release is detected RN is dis-
abled and C
X
begins to charge through the external resistor
(R
X
), providing a key-release debounce time
R
X
C
X
. This
charge time is again sensed by the Schmitt-trigger inverter,
enabling the scan clock to continue on the next high-to-low
transitions of TPB, after the current keycode data is read by
the CPU.
Dynamic Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
±
5%, Unless Otherwise Specified
PARAMETER
V
DD
(V)
LIMITS
UNITS
CDP1871AD, CDP1871AE
CDP1871ACD, CDP1871ACE
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Clock Cycle Time
t
CC
5
-
-
-
-
-
-
Note 2
10
-
-
-
-
-
-
Note 2
Clock Pulse Width High
t
CWH
5
100
40
-
100
40
-
ns
10
50
20
-
-
-
-
ns
Data Available Valid Delay
t
DAL
5
-
260
500
-
260
500
ns
10
-
130
250
-
-
-
ns
Data Available Invalid Delay
t
DAH
5
-
70
150
-
70
150
ns
10
-
35
75
-
-
-
ns
Scan Count Delay
(Non-Repeat)
t
CD1
5
-
850
1900
-
850
1900
ns
10
-
425
950
-
-
-
ns
Data Out Valid Delay
t
CDV
5
-
120
250
-
120
250
ns
10
-
60
125
-
-
-
ns
Data Out Hold Time
t
CDH
5
-
100
200
-
100
200
ns
10
-
50
100
-
-
-
ns
Repeat Valid Delay
t
RPL
5
-
150
400
-
150
400
ns
10
-
75
200
-
-
-
ns
Repeat Invalid Delay
t
RPH
5
-
350
700
-
350
700
ns
10
-
170
350
-
-
-
ns
NOTES:
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
2. t
CC
= t
CWH
+ t
CWL
t
CWL
= t
CD1
+ KC
k = 0.9ns per pF
c = Keyboard capacitance (pF)
CDP1871A, CDP1871AC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1871AE | CMOS Keyboard Encoder |
| CDP1874C | High-Speed 8-Bit Input and Output Ports(高速8位并行I/O端口) |
| CDP1872 | High-Speed 8-Bit Input and Output Ports |
| CDP1872C | High-Speed 8-Bit Input and Output Ports |
| CDP1872CE | High-Speed 8-Bit Input and Output Ports |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1871AE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Keyboard Encoder |
| CDP1872 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Speed 8-Bit Input and Output Ports |
| CDP1872C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Speed 8-Bit Input and Output Ports |
| CDP1872CD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CDP1872CE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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