參數資料
型號: CDP1855CEX
廠商: INTERSIL CORP
元件分類: 數字信號處理外設
英文描述: 8-Bit Programmable Multiply/Divide Unit
中文描述: 8-BIT, DSP-MULTIPLIER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數: 11/15頁
文件大小: 85K
代理商: CDP1855CEX
4-57
Y
Y
Y
Z
Z
Z
1
3
2
1
-------------------------------------------
Z
3
Z
2
Z
1
=
Y
Y
Y
1
3
2
X
1
---------------------
+
FIGURE 5. CASCADING THREE MDU’s (CDP1855) IN AN 1800 SYSTEM WITH MDU’s BEING ACCESSED AS I/O PORTS IN
PROGRAMMING EXAMPLE
FIGURE 6. CASCADING FOUR MDU’s (CDP1855)
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
C.O.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
DATA BUS
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
C.O.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
O.F.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
V
DD
EF1
BUS
MRD
TPB
CLEAR
N2
N1
N0
MOST SIGNIFICANT
LEAST SIGNIFICANT
OR
I/O SELECT
V
DD
8
8
8
CLOCK
8
TO
CPU
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
C.O.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
DATA BUS
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
C.O.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
C.O.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
C.I.
Z
R
Y
R
RA2
RA1
RA0
CTL
CE
CLR
STB
RD/
WE
BUS
CDP1855
O.F.
Z
L
Y
L
SHIFT
CLK
CN0
CN1
V
DD
V
DD
CLOCK
EF1
BUS
MRD
TPB
CLEAR
N2
N1
N0
MOST SIGNIFICANT
LEAST SIGNIFICANT
CDP1855, CDP1855C
相關PDF資料
PDF描述
CDP1855D 8-Bit Programmable Multiply/Divide Unit
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參數描述
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