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參數資料
| 型號： | CDP1854AQ |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| 中文描述： | 1 CHANNEL(S), 400K bps, SERIAL COMM CONTROLLER, PQCC44 |
| 文件頁數： | 17/21頁 |
| 文件大小： | 95K |
| 代理商： | CDP1854AQ |
5-58
Dynamic Electrical Specifications
T
A
= -40
o
C to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
(See Figure 9)
PARAMETER
V
DD
(V)
LIMITS
UNITS
CDP1854A
CDP1854AC
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
INTERFACE TIMING - MODE 0
Minimum Pulse Width
CRL
t
CRL
5
100
150
100
150
ns
10
50
75
-
-
ns
MR
t
MR
5
200
400
200
400
ns
10
100
200
-
-
ns
Minimum Setup Time
Control Word to CRL
t
CWC
5
40
80
40
80
ns
10
20
50
-
-
ns
Minimum Hold Time
Control Word after CRL
t
CCW
5
100
150
100
150
ns
10
50
75
-
-
ns
Propagation Delay Time
SFD High to SOD
t
SFDH
5
200
300
200
300
ns
10
100
150
-
-
ns
SFD Low to SOD
t
SFDL
5
75
120
75
120
ns
10
40
60
-
-
ns
RRD High to Receiver Register
High Impedance
t
RRDH
5
200
300
200
300
ns
10
100
150
-
-
ns
RRD Low to Receiver Register Active
t
RRDL
5
100
150
100
150
ns
10
50
75
-
-
ns
NOTES:
1. Typical values for T
A
= 25
o
C and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
FIGURE 9. MODE 0 INTERFACE TIMING DIAGRAM
t
CWC
CONTROL INPUT WORD TIMING
CONTROL WORD INPUT
CRL
STATUS OUTPUTS
SFD
STATUS OUTPUT TIMING
t
CRL
t
SFDH
R BUS 0
R BUS 7
RECEIVER REGISTER DISCONNECT TIMING
t
RRDH
RRD
t
RRDL
t
SFDL
t
CCW
CDP1854A, CDP1854AC
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相關代理商/技術參數 |
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| CDP1854A-Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| CDP1855_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit Programmable Multiply/Divide Unit |
| CDP1855C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit Programmable Multiply/Divide Unit |
| CDP1855CD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit Programmable Multiply/Divide Unit |
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