參數(shù)資料
型號: CDP1854AD
廠商: HARRIS SEMICONDUCTOR
元件分類: 微控制器/微處理器
英文描述: Programmable Universal Asynchronous Receiver/Transmitter (UART)
中文描述: 1 CHANNEL(S), 400K bps, SERIAL COMM CONTROLLER, CDIP40
文件頁數(shù): 12/21頁
文件大?。?/td> 95K
代理商: CDP1854AD
5-53
NOTES:
1. If a start bit occurs at a time less than t
DC
before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding
Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM
R CLOCK
READ
(NOTE 2)
t
CC
t
CL
t
CH
t
DC
1
2
START BIT
t
TDA
CLOCK 7 1/2
SAMPLE
3
4
5
6
7
16
(NOTE 1)
SDI
1
2
3
4
5
6
7
8
9
STOP BIT 1
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CDA
t
TT
t
COE
t
CPE
t
CFE
OE
PE
(NOTE 3)
FE
PARITY
DA
TPB
(NOTE 3)
NOTE:
1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.
FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
t
RSW
t
WRS
t
TT
t
WD
t
DW
TPB
(NOTE 1)
T BUS 0-
T BUS 7
RD/WR, CS2
(NOTE 1)
CS3, CS1
(NOTE 1)
RSEL
CDP1854A, CDP1854AC
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