參數(shù)資料
型號(hào): CDP1854ACQ
廠商: HARRIS SEMICONDUCTOR
元件分類: 微控制器/微處理器
英文描述: Programmable Universal Asynchronous Receiver/Transmitter (UART)
中文描述: 1 CHANNEL(S), 200K bps, SERIAL COMM CONTROLLER, PQCC44
文件頁數(shù): 20/21頁
文件大小: 95K
代理商: CDP1854ACQ
5-61
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
THC
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + t
CD
later.
FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM
T CLOCK
THRL
SDO
THRE
TSRE
T BUS 0
T BUS 7
t
CC
t
CL
t
CH
t
THC
1
2
t
THTH
t
CD
t
CT
t
TTS
t
TTHR
t
TD
t
DT
DATA
t
CD
1ST DATA BIT
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
3
4
5
6
7
14
15
16
1
2
3
NOTES:
1. If a start bit occurs at a time less than t
DC
before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
register, the OE signal will come true.
FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM
R CLOCK
R BUS 7
DA
DAR
t
CC
t
CL
t
CH
t
1
2
START BIT
t
DDA
t
CDV
CLOCK 7 1/2
SAMPLE
3
4
5
6
7
16
(NOTE 1)
SDI
1
2
3
4
5
6
7
8
9
STOP BIT 1
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CDA
t
DD
t
COE
t
CPE
t
CFE
R BUS 0 -
OE
PE
(NOTE 2)
FE
PARITY
FIGURE 12. SERIAL DATA WORD FORMAT
NEXT DATA WORD
STOP BITS 1, 1-1/2 OR 2
PARITY BIT
DATA
MSB
5 - 8 DATA BITS
DATA
LSB
START BIT
16 / f
CLOCK
CDP1854A, CDP1854AC
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