參數(shù)資料
型號(hào)： CDP1854A
廠商： Intersil Corporation
英文描述： Programmable Universal Asynchronous Receiver/Transmitter (UART)
中文描述： 可編程通用異步接收器/發(fā)送器（UART）
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 95K
代理商： CDP1854A
5-51
Dynamic Electrical Specifications
T
A
= -40
o
C to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
(See Figure 3)
PARAMETER
V
DD
(V)
LIMITS
UNITS
CDP1854A
CDP1854AC
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
TRANSMITTER TIMING - MODE 1
Minimum Clock Period
t
CC
5
250
310
250
310
ns
10
125
155
-
-
ns
Minimum Pulse Width
Clock Low Level
t
CL
5
100
125
100
125
ns
10
75
100
-
-
ns
Clock High Level
t
CH
5
100
125
100
125
ns
10
75
100
-
-
ns
TPB
t
TT
5
100
150
100
150
ns
10
50
75
-
-
ns
Minimum Setup Time
TPB to Clock
t
TC
5
175
225
175
225
ns
10
90
150
-
-
ns
Propagation Delay Time
Clock to Data Start Bit
t
CD
5
300
450
300
450
ns
10
150
225
-
-
ns
TPB to THRE
t
TTH
5
200
300
200
300
ns
10
100
150
-
-
ns
Clock to THRE
t
CTH
5
200
300
200
300
ns
10
100
150
-
-
ns
NOTES:
1. Typical values for T
A
= 25
o
C and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The Transmitter Shift Register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
TC
after
the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + t
CD
later.
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0.
FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1
T CLOCK
THRE
WRITE (TPB)
(NOTE 3)
SDO
t
CC
t
CL
t
CH
1
2
t
TTH
t
CD
t
CD
1ST DATA BIT
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
3
4
5
6
7
14
15
16
1
2
3
4
t
TT
t
CTH
t
TC
CDP1854A, CDP1854AC
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