- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379856 > CDP1853C (Intersil Corporation) High-Reliability CMOS N-Bit 1 of 8 Decoder PDF資料下載
參數(shù)資料
| 型號： | CDP1853C |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| 中文描述： | 高可靠性的CMOS N位的8解碼器1 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 35K |
| 代理商： | CDP1853C |
4-44
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . .
±
10mA
Thermal Resistance (Typical)
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
T
A
= Full Package Temperature Range
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T
A
)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Storage Temperature Range (T
STG
). . . . . . . . . . . .-65
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16
±
1/32 In. (1.59
±
0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . .+265
o
C
θ
JA
(
o
C/W)
85
θ
JC
(
o
C/W)
22
Timing Diagrams
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
FIGURE 2B. CE TO OUTPUT DELAY TIME
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
NOTE:
1. To measure T
AO
, Clock B must be tied low.
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
NOTE:
1. Output enabled when EN = high. Internal signal shown for refer-
ence only (see Figure 1).
FIGURE 3. TIMING DIAGRAM
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
N0 - N2
OUTPUT 0 - 7
T
N0
CE
OUTPUT 0 - 7
T
EOH
T
EOL
MIN. CLOCK B
PULSE WIDTH
OUTPUT 0 - 7
T
BO
CLOCK B
T
CBCB
T
AO
CLOCK A
OUTPUT 0 - 7
MIN. CLOCK A
PULSE WIDTH
T
CACA
(SEE NOTE 1)
TPA
TPB
CE
EN
OUTPUT
(NOTE 1)
A
B
C
CHIP ENABLE
V
DD
CLK A
N0
N1
OUT 0
OUT 1
OUT 2
OUT 3
N2
CE
OUT 4
OUT 5
OUT 6
OUT 7
CLK B
CDP1853/3, CDP1853C/3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
| CDP1853CDX | N-Bit 1 of 8 Decoder |
| CDP1853CE | N-Bit 1 of 8 Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1853C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:N-Bit 1 of 8 Decoder |
| CDP1853CD/B | 制造商:Rochester Electronics LLC 功能描述: |
| CDP1853CD3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3/B | 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。