參數(shù)資料
型號: CDP1851
廠商: Intersil Corporation
英文描述: CMOS Programmable I/O Interface(CMOS 可編程I/O接口)
中文描述: CMOS可編程I / O接口的CMOS(可編程的I / O接口)
文件頁數(shù): 7/14頁
文件大?。?/td> 56K
代理商: CDP1851
4-11
TABLE 4. (RA1 = 0, RA0 = 1)
INTERRUPT CONTROL
7
6
5
4
3
2
1
0
Interrupt Enable/Disable
INT
Enable
X
X
X
A/B
0
0
1
NOTES:
1. INT Enable = 1, INT Enabled
= 0, INT Disabled
2. A/B = 0, Port A
= 1, Port B
TABLE 5. (RA1 = 0, RA0 = 1)
7
6
5
4
3
2
1
0
Status Register
D7
D6
D5
D4
D3
D2
D1
D0
NOTES:
1. All Modes
(D0) B INT status (1 means set)
(D1) A INT status (1 means set)
2. Bidirectional Mode Only
(D2) 1 = A INT was caused by A STROBE
(D3) 1 = A INT was caused by B STROBE
3. Bit-Programmable Mode
(D4) A RDY input data
(D5) A STROBE input data
(D6) B RDY input data
(D7) B STROBE input data
TABLE 6. CPU CONTROLS
(NOTE 1)
CS
RA1
RA0
RD/WE
WR/RE
ACTION
0
X
X
X
X
No-op bus three-stated
X
0
0
X
X
No-op bus three-stated
X
X
X
0
0
No-op bus three-stated
X
X
X
1
1
No-op bus three-stated
X
X
X
1
1
No-op bus three-stated
1
0
1
1
0
Read status register (Note 1)
1
0
1
0
1
Load control register
1
1
0
1
0
Read port A (Note 1)
1
1
0
0
1
Load port A
1
1
1
1
0
Read port B (Note 1)
1
1
1
0
1
Load port B
NOTE:
1. Read = RD/WE = 1 and WR/RE = 0 is latched on trailing edge of CLOCK.
TABLE 7. MEMORY I/O USE
RD/WE INPUT
WR/RE INPUT
TPB INPUT
}
PIO Terminal
I/O Space
MRD
TPB
TPB
}
CPU Terminals
Memory Space
MWR
MRD
TPB
CDP1851, CDP1851C
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CDP1851CD CMOS Programmable I/O Interface
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