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參數(shù)資料
| 型號(hào)： | CDP1823E |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 128-Word x 8-Bit LSI Static RAM |
| 中文描述： | 128 X 8 STANDARD SRAM, 450 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 28K |
| 代理商： | CDP1823E |
6-27
+
Dynamic Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, C
L
= 100pF
PARAMETER
SYMBOL
V
DD
(V)
LIMITS
CDP1823
CDP1823C
UNITS
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
Read Cycle (See Figure 1)
Access Time From Address
Change
t
AA
5
-
275
450
-
275
450
ns
10
-
150
250
-
-
-
ns
Access Time From Chip
Select
t
DOA
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
MRD to Output Active
t
AM
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
Data Hold Time After Read
t
DOH
5
25
50
75
25
50
75
ns
10
15
25
40
-
-
-
ns
NOTES:
1. Typical values are at T
A
= 25
o
C and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
ADDRESS
t
AA
t
AM
t
DOA
t
DOH
MRD
CS2, CS3, CS5
CS1, CS4
DATA OUT
HIGH IMPEDANCE
VALID DATA
90%
10%
NOTE:
1. MWR is high during read operation. Timing measurement reference is 0.5 V
DD
.
FIGURE 1. READ CYCLE TIMING DIAGRAM
CDP1823, CDP1823C
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| CDP1823EX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CDP1824C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:32-Word x 8-Bit Static RAM |
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