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參數(shù)資料
| 型號： | CDP1823D |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | 128-Word x 8-Bit LSI Static RAM |
| 中文描述： | 128 X 8 STANDARD SRAM, 450 ns, CDIP24 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 28K |
| 代理商： | CDP1823D |
6-28
Dynamic Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
±
5%, t
R
, t
F
= 20ns, C
L
= 100pF
PARAMETER
SYMBOL
V
DD
(V)
LIMITS
CDP1823
CDP1823C
UNITS
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
Write Cycle (See Figure 2)
Write Recovery
t
WR
5
75
-
-
75
-
-
ns
10
50
-
-
-
-
-
ns
Write Cycle
t
WC
5
400
-
-
400
-
-
ns
10
225
-
-
-
-
-
ns
Write Pulse Width
t
WRW
5
200
-
-
200
-
-
ns
10
100
-
-
-
-
-
ns
Address Setup Time
t
AS
5
125
-
-
125
-
-
ns
10
75
-
-
-
-
-
ns
Data Setup Time
t
DS
5
100
-
-
100
-
-
ns
10
75
-
-
-
-
-
ns
Data Hold Time From MWR
t
DH
5
75
-
-
75
-
-
ns
10
50
-
-
-
-
-
ns
NOTES:
1. Typical values are at T
A
= 25
o
C and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
ADDRESS
t
WC
t
AS
t
WR
CS1, CS4
CS2, CS3, CS5
t
WRW
t
DS
t
DH
MWR
BUS 0-7
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
CDP1823, CDP1823C
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CDP1823E | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
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| CDP18243 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory |
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