參數(shù)資料
型號(hào): CDP1823CD3
廠商: HARRIS SEMICONDUCTOR
元件分類: DRAM
英文描述: High-Reliability CMOS 128-Word x 8-Bit Static RAM
中文描述: 128 X 8 STANDARD SRAM, 505 ns, CDIP24
文件頁(yè)數(shù): 4/6頁(yè)
文件大?。?/td> 28K
代理商: CDP1823CD3
6-34
Access Time from MRD (Note 1)
t
AM
5
-
310
-
435
ns
Data Hold Time After Read
t
DH
5
50
-
70
-
ns
NOTE:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications
t
R
, t
F
= 10ns, C
L
= 50pF
(Continued)
PARAMETER
SYMBOL
V
DD
(V)
LIMITS
UNITS
+25
o
C, -55
o
C
+125
o
C
MIN
MAX
MIN
MAX
ADDRESS
t
RC
t
AA
t
AM
(NOTE 1)
MRD
t
AC
CS2, CS3, CS5
CS1, CS4
t
DH
HIGH IMPEDANCE
VALID DATA
90%
10%
NOTES:
1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output.
2. MWR is high during read operation. Timing measurement reference is 0.5V
DD
.
FIGURE 1. READ CYCLE TIMING DIAGRAM
(NOTE 1)
Write Cycle Dynamic Electrical Specifications
t
R
, t
F
= 10ns, C
L
= 50pF
PARAMETER
SYMBOL
V
DD
(V)
LIMITS
UNITS
+25
o
C, -55
o
C
+125
o
C
(NOTE 2)
MIN
MAX
(NOTE 2)
MIN
MAX
Write Cycle
t
WC
5
280
-
400
-
ns
Address Setup Time (Note 1)
t
AS
5
70
-
100
-
ns
Address Hold Time
t
AH
5
70
-
100
-
ns
Write Pulse Width (Note 1)
t
WW
5
140
-
200
-
ns
Data to MWR Setup Time (Note 1)
t
DS
5
70
-
100
-
ns
CDP1823C/3
相關(guān)PDF資料
PDF描述
CDP1823 128-Word x 8-Bit LSI Static RAM
CDP1823CD 128-Word x 8-Bit LSI Static RAM
CDP1823CDX 128-Word x 8-Bit LSI Static RAM
CDP1823CE 128-Word x 8-Bit LSI Static RAM
CDP1823D 128-Word x 8-Bit LSI Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDP1823CDX 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM
CDP1823CE 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM
CDP1823D 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM
CDP1823E 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM
CDP1823EX 制造商:Rochester Electronics LLC 功能描述:- Bulk