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參數(shù)資料
| 型號： | CDP1822E |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 256-Word x 4-Bit LSI Static RAM |
| 中文描述： | 256 X 4 STANDARD SRAM, 450 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 45K |
| 代理商： | CDP1822E |
6-15
Chip-Select 1 Hold
t
CS1H
5
0
-
-
0
-
-
ns
10
0
-
-
0
-
-
ns
Chip-Select 2 Hold
t
CS2H
5
0
-
-
0
-
-
ns
10
0
-
-
0
-
-
ns
Output Disable Set-Up
t
ODS
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
NOTES:
1. Time required by a limit device to allow for indicated function.
2. Typical values are for T
A
= 25
o
C and nominal V
DD
.
Dynamic Electrical Specifications
At T
A
+ -40 to +85
o
C, V
DD
±
5%, Input t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
,
C
L
= 100 pF.
(Continued)
PARAMETER
TEST
CONDITIONS
LIMITS
UNITS
CD1822
CDP1822C
V
DD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
A0-A7
t
WC
t
CSIS
t
CSIH
t
CS2S
t
CS2H
t
ODS
t
DS
t
DH
t
WRW
t
AS
DON’T CARE
CHIP-SELECT 1
CHIP-SELECT 2
OUTPUT DISABLE
DI1-DI4
READ/WRITE
t
WR
DATA IN STABLE
NOTE: t
ODS
is required for common I/O operation only. For separate I/O operations, output disable is don’t care.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
(NOTE)
CDP1822, CDP1822C
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相關代理商/技術參數(shù) |
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|---|---|
| CDP1822EX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822R1252 | 制造商:Harris Corporation 功能描述: |
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| CDP1823 WAF | 制造商:Intersil Corporation 功能描述: |
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