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參數(shù)資料
| 型號(hào)： | CDP1822CEX |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 256-Word x 4-Bit LSI Static RAM |
| 中文描述： | 256 X 4 STANDARD SRAM, 450 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 45K |
| 代理商： | CDP1822CEX |
6-14
t
DOA1
t
DOA2
t
DOH1
t
RC
t
DOH3
t
AA
DATA OUT
VALID
HIGH
IMPEDANCE
HIGH
IMPEDANCE
CHIP-SELECT 1
A0 - A7
CHIP-SELECT 2
OUTPUT DISABLE
READ/WRITE
DATA OUT
t
DOH2
t
DOA3
FIGURE 1. READ CYCLE TIMING WAVEFORMS
Dynamic Electrical Specifications
At T
A
+ -40 to +85
o
C, V
DD
±
5%, Input t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
,
C
L
= 100 pF.
PARAMETER
TEST
CONDITIONS
LIMITS
UNITS
CD1822
CDP1822C
V
DD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
Read Cycle Times (Figure 2)
Write Cycle
t
WC
5
500
-
-
500
-
-
ns
10
300
-
-
-
-
-
ns
Address Setup
t
AS
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
Write Recovery
t
WR
5
50
-
-
50
-
-
ns
10
40
-
-
-
-
-
ns
Write Width
t
WRW
5
250
-
-
250
-
-
ns
10
150
-
-
-
-
-
ns
Input Data Setup Time
t
DS
5
250
-
-
250
-
-
ns
10
150
-
-
-
-
-
ns
Data Hold
t
DH
5
50
-
-
50
-
-
ns
10
40
-
-
-
-
-
ns
Chip-Select 1 Setup
t
CS1S
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
Chip-Select 2 Setup
t
CS2S
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
CDP1822, CDP1822C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1822CH DIE | 制造商:Harris Corporation 功能描述: |
| CDP1822D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822E | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822EX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822R1252 | 制造商:Harris Corporation 功能描述: |
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