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參數(shù)資料
| 型號： | CDP1821C3 |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| 中文描述： | 高可靠性的CMOS 1024字× 1位靜態(tài)存儲(chǔ)器 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 32K |
| 代理商： | CDP1821C3 |
6-8
Read Cycle Dynamic Electrical Specifications
t
R
, t
F
= 10ns, C
L
= 50pF
PARAMETER
SYMBOL
V
DD
(V)
-55
o
C, +25
o
C
+125
o
C
UNITS
MIN
MAX
MIN
MAX
Data Access Time (Note 1)
t
DA
5
-
190
-
255
ns
Read Cycle Time
t
RC
5
190
-
255
-
ns
Output Enable Time
t
EN
5
65
-
90
-
ns
Output Disable Time
t
DIS
5
-
65
-
90
ns
NOTE:
1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
NOTES:
1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
2. Chip-Select (CS) permitted to change from low to high level or remain low.
3. Read/Write (R/W) must be at a high level during all address transitions.
4. Don’t care.
5. Data-Out (DO) is a high impedance within t
DIS
ns after the falling edge of R/W or the rising edge of CS.
FIGURE 1. READ CYCLE TIMING DIAGRAM
CS
A0 - A9
R/W
DATA OUT
(NOTE 5)
(NOTE 3)
(NOTE 1)
(NOTE 2)
(NOTE 4)
(NOTE 5)
HIGH
IMPEDANCE
DATA OUT
VALID
t
DOH
t
DOA
t
RC
t
AA
CDP1821C/3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1821CD3 | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| CDP1822C | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822C3 | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822 | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CD | 256-Word x 4-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1821CD | 制造商:Harris Corporation 功能描述: |
| CDP1821CD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1821CD3R1783 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1821D | 制造商:Harris Corporation 功能描述: |
| CDP1822 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
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