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參數(shù)資料
| 型號： | CDP1802BCE |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 8-Bit Microprocessors |
| 中文描述： | 8-BIT, 5 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 44K |
| 代理商： | CDP1802BCE |
3-35
NOTES:
6. This timing diagram is used to show signal relationships only, and does not represent any specific machine cycle.
7. All measurements are referenced to 50% point of the waveforms.
8. Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.
FIGURE 2. TIMING WAVEFORMS
0
2
3
4
5
6
7
0
00
10
20
30
40
50
60
70
00
01
11
21
31
41
51
61
71
01
t
W
CLOCK
t
PLH
t
PHL
TPA
TPB
t
SU
t
H
t
PLH
t
PHL
t
PLH,
t
P
H
L
LOW ORDER
ADDRESS BYTE
MEMORY
ADDRESS
t
PLH
MRD
(MEMORY
READ CYCLE)
t
PHL
t
PLH
t
PLH
t
PHL
t
PHL
MWR
(MEMORY
WRITE CYCLE)
DATA FROM
CPU TO BUS
STATE
CODES
t
PLH
t
PHL
t
PLH
t
PHL
Q
t
PLH,
t
PHL
N0, N1, N2
(I/O
EXECUTION
CYCLE)
t
PLH
DATA
LATCHED IN CPU
DATA FROM
BUS TO CPU
t
H
DMA
INTERRUPT
SAMPLED (S1, S2)
t
SU
t
H
t
SU
t
H
DMA
REQUEST
INTERRUPT
REQUEST
FLAG LINES
SAMPLED (IN SI)
EF 1-4
t
SU
t
H
WAIT
CLEAR
t
W
t
SU
ANY NEGATIVE
TRANSITION
t
PLH,
t
PHL
t
PLH
t
PHL
SAMPLED (S1, S2, S3)
t
SU
1
HIGH ORDER
ADDRESS BYTE
t
PLH,
t
PHL
t
PLH,
t
P
H
L
CDP1802AC/3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1802BCEX | CMOS 8-Bit Microprocessors |
| CDP1802BCQ | CMOS 8-Bit Microprocessors |
| CDP1802ACD3 | High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802A | CMOS 8-Bit Microprocessors |
| CDP1805 | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1802BCEX | 制造商:Harris Corporation 功能描述: |
| CDP1802BCQ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
| CDP1802CD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1802CD/3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| CDP1802CDX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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