參數(shù)資料
型號(hào)： CDCVF857RHA
廠商： Texas Instruments, Inc.
英文描述： 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
中文描述： 2.5 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器
文件頁(yè)數(shù)： 5/19頁(yè)
文件大?。?/td> 475K
代理商： CDCVF857RHA
SCAS047D MARCH 2003 REVISED JUNE 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
DGG
RHA/RTB
GQL
AGND
17
9
H1
Ground for 2.5
-
V analog supply
2.5
-
V analog supply
Differential clock input
AVDD
CLK, CLK
16
8
G2
13, 14
5, 6
F1, F2
I
FBIN, FBIN
35, 36
25, 26
F5, F6
I
Feedback differential clock input
FBOUT, FBOUT
32, 33
21, 22
H6, G5
O
Feedback differential clock output
GND
1, 7, 8, 18, 24,
25, 31, 41, 42, 48
1, 10
A3, A4, C1, C2, C5,
C6, H2, H5, K3, K4
Ground
PWRDWN
37
27
E6
I
Output enable for Y and Y
VDDQ
4, 11, 12, 15, 21,
28, 34, 38, 45
4, 7, 13, 18, 23,
24, 28, 33, 38
B3, B4, E1, E2, E5,
G1, G6, J3, J4
2.5-V supply
Y0, Y0
3, 2
37, 36
A1, A2
O
Y1, Y1
5, 6
39, 40
B2, B1
O
Y2, Y2
10, 9
3, 2
D1, D2
O
Y3, Y3
20, 19
12,11
J2, J1
O
Y4, Y4
22, 23
14, 15
K1, K2
O
Buffered output copies of input clock, CLK, CLK
Y5, Y5
46, 47
34, 35
A6, A5
O
Y6, Y6
44, 43
32, 31
B5, B6
O
Y7, Y7
39, 40
29, 30
D6, D5
O
Y8, Y8
29, 30
19, 20
J5, J6
O
Y9, Y9
27, 26
17, 16
K6, K5
O
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
DDQ
,
AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Notes 1 and 2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DDQ
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DDQ
)
Continuous output current, I
O
(V
O
= 0 to V
DDQ
)
Continuous current to GND or V
DDQ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.5 V to 3.6 V
–
0.5 V to V
DDQ
+ 0.5 V
–
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
±
50 mA
±
50 mA
±
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–
65
°
C to 150
°
C
JA For TSSOP (DGG) Package (see Note 3)
Airflow
Low K
89.1
°
C/W
150 ft/min
78.5
°
C/W
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4. Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the
θ
JA to 114.8
°
C/W (0 airflow).
JA For MLF (RHA/RTB) Package
Airflow
With 4 Thermal Vias
JA For BGA(GQL) Package (see Note 4)
Airflow
High K
70
°
C/W
65.3
°
C/W
High K
132.2
°
C/W
126.4
°
C/W
0 ft/min
0 ft/min
44.7
°
C/W
0 ft/min
150 ft/min
150 ft/min
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CDCVF857RHARG4 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
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CDCVF857RHATG4 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
CDCVF857RTB 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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