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參數(shù)資料
| 型號： | CDCVF857GQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 2.5 V的鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 475K |
| 代理商： | CDCVF857GQL |
SCAS047D MARCH 2003 REVISED JUNE 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
120
MAX
140
UNIT
Without load
fO = 170 MHz
fO = 200 MHz
fO = 170 MHz
fO = 200 MHz
fO = 170 MHz
fO = 200 MHz
125
150
IDD
Dynamic current on VDDQ
Differential outputs terminated with
120
/CL = 0 pF
220
270
mA
230
280
Differential outputs terminated with
120
/CL = 14 pF
VDDQ = 2.5 V, VI = VDDQ or GND
280
330
300
350
C
Part-to-part input capacitance variation
1
pF
CI(
)
All typical values are at a respective nominal VDDQ.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
Input capacitance difference between
CLK and CKB, FBIN, and FBINB
VDDQ = 2.5 V, VI = VDDQ or GND
0.25
pF
MIN
60
MAX
220
UNIT
fCLK
Operating clock frequency
MHz
Application clock frequency
90
220
Input clock duty cycle
Stabilization
time (PLL mode)
Stabilization
time (bypass mode)
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
40%
60%
10
μ
s
30
ns
switching characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
Low-to-high level propagation delay time
Test mode/CLK to any output
3.5
ns
High-to-low level propagation delay time
Test mode/CLK to any output
3.5
ns
tjit(per)
Jitter (period), See Figure 7
100 MHz (PC1600)
65
65
ps
133/167/200 MHz (PC2100/2700/3200)
30
30
tjit(cc)
Jitter (cycle-to-cycle), See Figure 4
100 MHz (PC1600)
50
50
ps
133/167/200 MHz (PC2100/2700/3200)
35
35
tjit(hper)
Half-period jitter, See Figure 8
100 MHz (PC1600)
100
100
ps
133/167/200 MHz (PC2100/2700/3200)
Load: 120
/14 pF
100/133/167/200 MHz
Load: 120
/14 pF
75
75
tslr(o)
t()
tsk(o)
§Refers to the transition of the noninverting output.
This parameter is assured by design but can not be 100% production tested.
Output clock slew rate, See Figure 9
1
2
V/ns
Static phase offset, See Figure 5
–50
50
ps
Output skew, See Figure 6
100/133/167/200 MHz
40
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCVF857GQLR | 功能描述:時鐘驅(qū)動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| CDCVF857RHAR | 功能描述:時鐘驅(qū)動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHARG4 | 功能描述:時鐘驅(qū)動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHAT | 功能描述:時鐘驅(qū)動器及分配 2.5V Ph Lock Loop DDR Clock Dr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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