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參數資料
| 型號： | CDCV855I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 2.5 V的鎖相環(huán)時鐘驅動器 |
| 文件頁數： | 4/10頁 |
| 文件大小： | 137K |
| 代理商： | CDCV855I |
CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A
–
SEPTEMBER 2001
–
REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input voltage
All inputs
VDDQ = 2.3 V,
VDDQ = min to max, IOH =
–
1 mA
VDDQ = 2.3 V,
VDDQ = min to max, IOL = 1 mA
VDDQ = 2.3 V,
VDDQ = 2.3 V,
VDDQ = 2.3 V,
II =
–
18 mA
–
1.2
V
VOH
High level output voltage
High-level output voltage
VDDQ
–
0.1
V
IOH =
–
12 mA
1.7
VOL
Low level output voltage
Low-level output voltage
0.1
V
IOL = 12 mA
VO = 1 V
VO = 1.2 V
0.6
IOH
IOL
VOD
High-level output current
–
18
–
32
mA
Low-level output current
26
35
mA
Output voltage swing
Differential outputs are terminated with
120
1.1
VDDQ
–
0.4
VOX
Output differential
cross-voltage
VDDQ/2
–
0.2
VDDQ/2
VDDQ/2 + 0.2
V
II
Input current
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
±
10
μ
A
IOZ
High-impedance-state output
current
VDDQ = 2.7 V,
VO = VDDQ or GND
±
10
μ
A
IDD(PD)
Power-down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ
of IDD and AIDD
Differential outputs
are terminated with
120
/ CL = 14 pF
Differential outputs
are terminated with
120
/ CL = 0 pF
fO = 167 MHz
VDDQ = 2.5 V
VI = VDDQ or GND
VDDQ = 2.5 V
VO = VDDQ or GND
100
200
μ
A
IDD
Dynamic current on VDDQ
fO = 167 MHz
150
180
mA
130
160
AIDD
CI
CO
All typical values are at respective nominal VDDQ.
Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.
Supply current on AVDD
Input capacitance
8
10
mA
2
2.5
3
pF
Output capacitance
2.5
3
3.5
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
MIN
60
MAX
180
UNIT
MHz
fCLK
Operating clock frequency
Input clock duty cycle
Stabilization
time (PLL mode)
Stabilization
time (Bypass mode)
§
Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND).
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
40%
60%
10
μ
s
30
ns
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CDCV855IPW | 功能描述:時鐘驅動器及分配 1:4 DDR PLL CLOCK DRIVERS RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV855IPWG4 | 功能描述:時鐘驅動器及分配 1:4 DDR PLL CLOCK DRIVERS RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV855IPWR | 功能描述:時鐘驅動器及分配 1:4 DDR PLL CLOCK DRIVERS RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV855IPWRG4 | 功能描述:時鐘驅動器及分配 1:4 DDR PLL CLOCK DRIVERS RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV855PW | 功能描述:時鐘驅動器及分配 1:4 DDR PLL CLOCK DRIVERS RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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