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參數(shù)資料
| 型號： | CDCU877GQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8V PHASE LOCK LOOP CLOCK DRIVER |
| 中文描述： | 1.8鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CDCU877GQL |
SCAS688A JUNE 2003 REVISED JANUARY 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 1)
AV
DD
, V
DD
= 1.8 V
±
0.1 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ten
tdis
tjit(cc+)
tjit(cc)
tjit(cc+)
tjit(cc)
t(
)
t(
)dyn
tsk(o)
Enable time, OE to any Y/Y
See Figure 11
8
ns
Disable time, OE to any Y/Y
See Figure 11
8
ns
Cycle-to-cycle period jitter (see Note 8)
160 MHz to 190 MHz, see Figure 4
0
40
ps
0
40
Cycle-to-cycle period jitter (see Note 8)
190 MHz to 340 MHz, see Figure 4
0
30
ps
0
30
Static phase offset time (see Note 2)
See Figure 5
50
50
ps
Dynamic phase offset time
See Figure 10
15
15
ps
Output clock skew
See Figure 6
35
ps
tjit(per)
Period jitter (see Notes 3 and 8)
160 MHz to 190 MHz, see Figure 7
30
30
ps
190 MHz to 340 MHz, see Figure 7
20
20
ps
160 MHz to 190 MHz, see Figure 8
115
115
ps
tjit(hper)
Half-period jitter (see Notes 3 and 8)
190 MHz to 250 MHz, see Figure 8
70
70
ps
250 MHz to 300 MHz, see Figure 8
40
40
ps
300 MHz to 340 MHz, see Figure 8
60
60
ps
Slew rate, OE
See Figure 3 and Figure 9
0.5
V/ns
SR
Input clock skew rate
See Figure 3 and Figure 9
1
2.5
4
V/ns
Output clock slew rate
(see Notes 4 and 5)
See Figure 3 and Figure 9
1.5
2.5
3
V/ns
VOX
Output differential-pair cross voltage
(see Note 6)
See Figure 2, CDCU877
(VDDQ/2)
0.1
(VDDQ/2)
+ 0.1
V
See Figure 2, CDCU877A (see Note 7)
(085
°
C)
(VDDQ/2)
0.1
(VDDQ/2)
+ 0.1
SSC modulation frequency
30
33
kHz
SSC clock input frequency deviation
0%
0.5%
PLL loop bandwidth
2
MHz
NOTES:
1. There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input
and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal
length cables must be used.
2. Phase static offset time does not include jitter.
3. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other.
4. The output slew rate is determined from the IBIS model into the load shown in Figure 3.
5. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and
feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended
target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the
requirements of the registered DDR2 DIMM application.
6. Output differential-pair cross voltage specified at the DRAM clock input or the test load.
7. VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application.
8. This parameter is assured by design and characterization.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDCU877GQLR | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877GQLT | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877RHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| CDCU877RHAR | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877RHARG4 | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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