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參數(shù)資料
| 型號： | CDC9171 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DVD System Clock Synthesizerers(DVD系統(tǒng)時鐘合成器) |
| 中文描述： | DVD系統(tǒng)時鐘Synthesizerers（影碟系統(tǒng)時鐘合成器） |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 95K |
| 代理商： | CDC9171 |
CDC9171
DVD SYSTEM CLOCK SYNTHESIZER
SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
VI
VIH
VIL
IOH
IOL
TA
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage
3
3.6
V
Input voltage (PWRDN only)
0
5.5
V
High-level input voltage
2
V
Low-level input voltage
0.8
V
High-level output current
–8
mA
Low-level output current
8
mA
°
C
Operating free-air temperature
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
°
C
TYP
MIN
MAX
UNIT
MIN
MAX
VIK
VOH
VOL
II
VCC = 3 V,
VCC = 3 V,
VCC = 3 V,
VCC = 3.6 V,
II = –18 mA
IOH = –8 mA
IOL = 8 mA
VI = VCC or GND
–1.2
–1.2
V
2.4
2.4
V
0.4
±
1
0.4
±
1
V
μ
A
ICC
VCC = 3.6 V,
VCC 3.6 V,
VI = VCC or GND
IO = 0
IO 0
Outputs active
(PWRDN = H)
20
35
35
mA
Outputs low
(PWRDN = L)
5
10
10
Ci
Co
VI = 3 V or 0
VO = 3 V or 0
7
pF
8
pF
Except for crystal input (1X1)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Stabilization time
After PWRDN
↑
After power up
5
5
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at 1X1.
switching characteristics over recommended free-air temperature range for 3-V outputs (see
Figure 1)
§
PARAMETER
VCC = 3.3 V,
TA = 25
°
C
MIN
VCC = 3 V to 3.6 V,
TA = 0
°
C to 70
°
C
MIN
UNIT
MAX
MAX
±
200
±
250
55%
Jitter
FCLK1
ps
All other outputs
Duty cycle
tr
tf
Any output
45%
Any output (CL = 20 pF)
Any output (CL = 20 pF)
2.5
ns
2.5
ns
§Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the test circuit shown in Figure 1.
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