參數(shù)資料
型號: CDC509PW
廠商: Texas Instruments, Inc.
英文描述: 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
中文描述: 3.3 - V相位鎖相環(huán)時鐘驅(qū)動器
文件頁數(shù): 5/9頁
文件大小: 132K
代理商: CDC509PW
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 5 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.165 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tphase error, reference
(see Figure 3)
66 MHz < CLKIN
< 100
MHz
FBIN
100...480
ps
tphase error, – jitter,
(see Note 6)
tsk(o)
Jitter(pk-pk)
Duty cycle, reference
y y
(see Figure 4)
CLKIN
= 100 MHz
FBIN
220
480
340
ps
Any Y or FBOUT
Any Y or FBOUT
200
ps
F(clkin > 66 MHz)
F(clkin
66 MHz)
F(clkin > 66 MHz)
Any Y or FBOUT
–100
100
ps
Any Y or FBOUT
45%
55%
Any Y or FBOUT
43%
57%
tr
tf
Any Y or FBOUT
1.1
1.5
0.7
1.6
ns
Any Y or FBOUT
0.8
1.3
0.5
1.5
ns
This parameters are not production tested.
The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% VCC range.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tpd
50% VCC
3 V
0 V
VOH
VOL
Input
0.4 V
2 V
tr
tf
0.4 V
2 V
Output
500
50% VCC
30 pF
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
100 MHz, ZO = 50
, tr
1.2 ns, tf
1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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