參數(shù)資料
型號: CDC2510BPW
廠商: Texas Instruments, Inc.
英文描述: 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
中文描述: 3.3 - V相位鎖相環(huán)時鐘驅(qū)動器
文件頁數(shù): 8/10頁
文件大小: 146K
代理商: CDC2510BPW
CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
PHASE ERROR
vs
SUPPLY VOLTAGE
300
250
150
100
50
0
200
P
2.9
3.0
3.1
VCC – Supply Voltage – V
3.2
3.3
3.4
3.5
3.6
3.7
350
400
–50
–100
fc = 100 MHz
CLY = CLF = 30 pF
TA = 25
°
C
Phase Error Measured
from CLK to FBIN
Figure 6
JITTER
vs
CLOCK FREQUENCY
400
300
250
200
0
350
J
35
45
55
fc – Clock Frequency – MHz
65
75
85
95
105 115 125
150
100
50
Cycle to Cycle
Peak to Peak
VCC = 3.3 V
TA = 25
°
C
Figure 7
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
12
10
6
4
2
0
8
10
20
40
60
80
100
120
140
14
16
AVCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
TA = 25
°
C
fc – Clock Frequency – MHz
A
Figure 8
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
150
100
50
0
200
10
20
40
60
80
100
120
140
VCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
TA = 25
°
C
I
fc – Clock Frequency – MHz
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
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