參數(shù)資料
型號(hào): CDB4364
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 30/50頁(yè)
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS4364
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 6
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: CS4364
相關(guān)產(chǎn)品: CS4364-CQZR-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
598-1059-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
36
DS619F1
CS4364
6.4.2
Direct DSD Conversion (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available
(see Section 2 for filter specifications).
6.4.3
Static DSD Detect (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
6.4.4
Invalid DSD Detect (INVALID_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
6.4.5
DSD Phase Modulation Mode Select (DSD_PM_MODE)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.
6.4.6
DSD Phase Modulation Mode Enable (DSD_PM_EN)
Function:
When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
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