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參數(shù)資料
| 型號： | CD74HCT7046AM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | GREEN, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 485K |
| 代理商： | CD74HCT7046AM |
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4
quency is lower than the COMPIN frequency, then it is the n-
type driver that is held “ON” for most of the cycle. Subse-
quently, the voltage at the capacitor (C2) of the low-pass filter
connected to PC2OUT varies until the signal and comparator
inputs are equal in both phase and frequency. At this stable
point the voltage on C2 remains constant as the PC2 output is
in three-state and the VCO input at pin 9 is a high impedance.
Thus, for PC2, no phase difference exists between SIGIN
and COMPIN over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass lter is
reduced because both p-type and n-type drivers are “OFF”
for most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass lter.
With no signal present at SIGIN, the VCO adjusts, via PC2,
to its lowest frequency.
Lock Detector Theory of Operation
Detection of a locked condition is accomplished by a NOR
gate and an envelope detector as shown in Figure 6. When
the PLL is in Lock, the output of the NOR gate is High and
the lock detector output (Pin 1) is at a constant high level. As
the loop tracks the signal on Pin 14 (signal in), the NOR gate
outputs pulses whose widths represent the phase differ-
ences between the VCO and the input signal. The time
between pulses will be approximately equal to the time con-
stant of the VCO center frequency. During the rise time of
the pulse, the diode across the 1.5k
resistor is forward
biased and the time constant in the path that charges the
lock detector capacitor is T = (150
x CLD).
During the fall time of the pulse the capacitor discharges
through the 1.5k
and the 150 resistors and the channel
resistance of the n-device of the NOR gate to ground
(T = (1.5k
+ 150 + Rn-channel) x CLD).
The waveform preset at the capacitor resembles a sawtooth
as shown in Figure 7. The lock detector capacitor value is
determined by the VCO center frequency. The typical range
of capacitor for a frequency of 10MHz is about 10pF and for
a frequency of 100kHz is about 1000pF. The chart in Figure
8 can be used to select the proper lock detector capacitor
value. As long as the loop remains locked and tracking, the
level of the sawtooth will not go below the switching thresh-
old of the Schmitt-trigger inverter. If the loop breaks lock, the
width of the error pulse will be wide enough to allow the saw-
tooth waveform to go below threshold and a level change at
the output of the Schmitt trigger will indicate a loss of lock,
as shown in Figure 9. The lock detector capacitor also acts
to lter out small glitches that can occur when the loop is
either seeking or losing lock.
Note: When using phase comparator 1, the detector will only
indicate a lock condition on the fundamental frequency and
not on the harmonics, which PC1 will also lock on. If a detec-
tion of lock is needed over the harmonic locking range of
PC1, then the lock detector output must be OR-ed with the
output of PC1.
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN - φCOM-
PIN); φDEMOUT = (φSIGIN - φCOMPIN)
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT fo
VCC
VDEMOUT (AV)
1/2 VCC
0
0o
90o
φ
DEMOUT
180o
SIGIN
COMPIN
VCOOUT
PC1OUT
VCOIN
VCC
GND
CD74HC7046A, CD74HCT7046A
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| CD74HCT7046AM96G4 | 功能描述:鎖相環(huán) - PLL Hi Spd CMOS LogPh- Locked Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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