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參數(shù)資料
| 型號： | CD74HCT7046 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Phase-Locked Loop with VCO and Lock Detector |
| 中文描述： | 鎖相環(huán)與VCO和鎖定檢測回路 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 302K |
| 代理商： | CD74HCT7046 |
3
General Description
VCO
The VCO requires one external capacitor C1 (between C1
A
and C1
B
) and one external resistor R1 (between R1 and
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter-
mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia-
gram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro-
vided at pin 10 (DEM
OUT
). In contrast to conventional tech-
niques where the DEM
OUT
voltage is one threshold voltage
lower than the VCO input voltage, here the DEM
OUT
voltage
equals that of the VCO input. If DEM
OUT
is used, a load
resistor (R
S
) should be connected from DEM
OUT
to Gnd; if
unused, DEM
OUT
should be left open. The VCO output
(VCO
OUT
) can be connected directly to the comparator
input (COMP
IN
), or connected via a frequency-divider. The
VCO output signal has a specified duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.
Phase Comparators
The signal input (SIG
IN
) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci-
tive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f
i
) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f
r
= 2f
i
) is suppressed, is:
V
DEMOUT
= (V
CC
/
π
) (
φ
SIGIN
-
φ
COMPIN
) where V
DEMOUT
is the demodulator output at pin 10; V
DEMOUT
= V
PC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (V
DEMOUT
), is the resultant of the phase differences
of signals (SIG
IN
) and the comparator input (COMP
IN
) as
shown in Figure 2. The average of V
DEM
is equal to 1/2 V
CC
when there is no signal or noise at SIG
IN
, and with this input
the VCO oscillates at the center frequency (f
o
). Typical wave-
forms for the PC1 loop locked at f
o
shown in Figure 3.
The frequency capture range (2f
c
) is defined as the fre-
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2f
L
) is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIGIN and COMP
IN
are not important. PC2 comprises two
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIG
IN
causes an up-count and COMP
IN
a down-
count. The transfer function of PC2, assuming ripple (f
r
= f
i
)
is suppressed, is:
V
DEMOUT
= (V
CC
/4
π
) (
φ
SIGN
-
φ
COMPIN
) where V
DEMOUT
is the demodulator output at pin 10; V
DEMOUT
= V
PC2OUT
(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
DEMOUT
), is the resultant of the phase differences of
SIG
IN
and COMP
IN
as shown in Figure 4. Typical waveforms
for the PC2 loop locked at f
o
are shown in Figure 5.
When the frequencies of SIG
IN
and COMP
IN
are equal but
the phase of SIG
IN
leads that of COMP
IN
, the p-type output
driver at PC2
OUT
is held “ON” for a time corresponding to
the phase differences (
φ
DEMOUT
). When the phase of SIG
IN
lags that of COMP
IN
, the n-type driver is held “ON”.
When the frequency of SIG
IN
is higher than that of COMP
IN
,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n-type
and p-type drivers are “OFF” (three-state). If the SIG
IN
fre-
Pin Descriptions
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LD
Lock Detector Output (Active High)
2
PC1
OUT
Phase Comparator 1 Output
3
COMP
IN
Comparator Input
4
VCO
OUT
VCO Output
5
INH
Inhibit Input
6
C1
A
Capacitor C1 Connection A
7
C1
B
Capacitor C1 Connection B
8
Gnd
Ground (0V)
9
VCO
IN
VCO Input
10
DEM
OUT
Demodulator Output
11
R
1
Resistor R1 Connection
12
R
2
Resistor R2 Connection
13
PC2
OUT
Phase Comparator 2 Output
14
SIG
IN
Signal Input
15
C
LD
Lock Detector Capacitor Input
16
V
CC
Positive Supply Voltage
CD74HC7046A, CD74HCT7046A
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