參數(shù)資料
型號(hào): CD74HC4040NSR
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: High-Speed CMOS Logic 12-Stage Binary Counter
中文描述: 高速CMOS邏輯12位的二進(jìn)制計(jì)數(shù)器
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 346K
代理商: CD74HC4040NSR
7
Q
n
to Q
n
+ 1
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
C
L
=15pF
5
-
4
-
-
-
-
-
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
40
-
50
-
60
ns
C
L
=15pF
5
-
17
-
-
-
-
-
ns
Output Transition
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
IN
C
L
=15pF
-
-
-
10
-
10
-
10
pF
Power Dissipation
Capacitance (Notes 3, 4)
C
PD
C
L
=15pF
5
-
45
-
-
-
-
-
pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per package.
4. P
D
= V
CC2
f
i
+
(C
L
V
CC2
fi/M) where: M = 2
1
, 2
2
, 2
3
, ...2
12
, f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications
Input t
r
, t
f
= 6ns
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
10%
50%
t
WL
t
WH
t
WL
+ t
WH
=fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
0.3V
1.3V
t
WL
t
WH
t
WL
+ t
WH
=fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040
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